CLA100PD1200NA
Phase leg
High Efficiency Thyristor
4 3 21
Part number
CLA100PD1200NA
Backside: Isolated
TAV
T
V V1,21
RRM
100
1200
=
V=V
I=A
2x
Features / Advantages: Applications: Package:
● Thyristor for line frequency
● Planar passivated chip
● Long-term stability
● Line rectifying 50/60 Hz
● Softstart AC motor control
● DC Motor control
● Power converter
● AC power control
● Lighting and temperature control
SOT-227B (minibloc)
● Industry standard outline
● RoHS compliant
● Epoxy meets UL 94V-0
● Base plate: Copper
internally DCB isolated
● Advanced power cycling
● Isolation Voltage: V~
3000
The data contained in this product data sheet is exclusively intended for technically trained staff. The user will have to evaluate the suitability of the product for the intended application and
the completeness of the product data with respect to his application. The specifications of our components may not be considered as an assurance of component characteristics. The
information in the valid application- and assembly notes must be considered. Should you require product information in excess of the data given in this product data sheet or which concerns
the specific application of your product, please contact the sales office, which is responsible for you.
Due to technical requirements our product may contain dangerous substances. For information on the types in question please contact the sales office, which is responsible for you.
Should you intend to use the product in aviation, in health or live endangering or life support applications, please notify. For any such application we urgently recommend
- to perform joint risk and quality assessments;
- the conclusion of quality agreements;
- to establish joint measures of an ongoing product survey, and that we may make delivery dependent on the realization of any such measures.
Terms Conditions of usage:
IXYS reserves the right to change limits, conditions and dimensions. 20150827bData according to IEC 60747and per semiconductor unless otherwise specified
© 2015 IXYS all rights reserved
CLA100PD1200NA
V = V
kA²s
kA²s
kA²s
kA²s
Symbol
Definition
Ratings
typ.
max.
I
V
IA
V
T
1,27
R0,35 K/W
min.
100
VV
50T = 25°C
VJ
T = °C
VJ
mA2V = V
T = 25°C
VJ
I = A
T
V
T = °C
C
85
P
tot
350 WT = 25°C
C
100
1200
forward voltage drop
total power dissipation
Conditions
Unit
1,55
T = 25°C
VJ
125
V
T0
V0,83T = °C
VJ
150
r
T
3,7 mΩ
V1,21T = °C
VJ
I = A
T
V
100
1,58
I = A200
I = A200
threshold voltage
slope resistance for power loss calculation only
µA
125
VV1200T = 25°C
VJ
IA150
P
GM
Wt = 30 µs 10
max. gate power dissipation
P
T = °C
C
150
Wt = 5
P
P
GAV
W0,5
average gate power dissipation
C
J
77
junction capacitance
V = V400 T = 25°Cf = 1 MHz
RVJ
pF
I
TSM
t = 10 ms; (50 Hz), sine T = 45°C
VJ
max. forward surge current
T = °C
VJ
150
I²t T = 45°C
value for fusing
T = °C150
V = 0 V
R
V = 0 V
R
V = 0 V
V = 0 V
t = 8,3 ms; (60 Hz), sine
t = 10 ms; (50 Hz), sine
t = 8,3 ms; (60 Hz), sine
t = 10 ms; (50 Hz), sine
t = 8,3 ms; (60 Hz), sine
t = 10 ms; (50 Hz), sine
t = 8,3 ms; (60 Hz), sine
VJ
R
VJ
R
thJC
thermal resistance junction to case
T = °C
VJ
150
1,50
1,62
8,13
7,87
kA
kA
kA
kA
1,28
1,38
11,3
10,9
1200
300 µs
RMS forward current
T(RMS)
TAV
180° sine
average forward current
(di/dt)
cr
A/µs
150repetitive, I =T
VJ
= 150 °C; f = 50 Hz
critical rate of rise of current
V
GT
gate trigger voltage
V = 6 V T = °C25
(dv/dt) T = 150°C
critical rate of rise of voltage
A/µs500
V/µs
t = µs;
I A; V = ⅔ V
R = ∞; method 1 (linear voltage rise)
VJ
DVJ
300 A
T
P
G
= 0,5
di /dt A/µs;
G
=0,5
DRM
cr
V = ⅔ V
DRM
GK
1000
1,5 V
T = °C-40
VJ
I
GT
gate trigger current
V = 6 V T = °C25
DVJ
40 mA
T = °C-40
VJ
1,6 V
80 mA
V
GD
gate non-trigger voltage
T = °C
VJ
0,2 V
I
GD
gate non-trigger current
5 mA
V = ⅔ V
D DRM
150
latching current
T = °C
VJ
150 mA
I
L
25t µs
p
=10
I A;
G
= 0,5 di /dt A/µs
G
= 0,5
holding current
T = °C
VJ
100 mA
I
H
25V = 6 V
D
R = ∞
GK
gate controlled delay time
T = °C
VJ
2 µs
t
gd
25
I A;
G
= 0,5 di /dt A/µs
G
= 0,5
V = ½ V
D DRM
turn-off time
T = °C
VJ
150 µs
t
q
di/dt = A/µs10 dv/dt = V/µs20
V =
R
100 V; I A;
T
= 100 V = ⅔ V
DRM
tµs
p
= 200
non-repet., I = 100 A
T
125
R
thCH
0,10
thermal resistance case to heatsink
K/W
Rectifier
1300
RRM/DRM
RSM/DSM
max. non-repetitive reverse/forward blocking voltage
max. repetitive reverse/forward blocking voltage
R/D
reverse current, drain current
T
T
R/D
R/D
200
IXYS reserves the right to change limits, conditions and dimensions. 20150827bData according to IEC 60747and per semiconductor unless otherwise specified
© 2015 IXYS all rights reserved
CLA100PD1200NA
Ratings
abcdZyyww
XXXXX
Product Marking
Logo
Part No.
DateCode
Assembly Code
Assembly Line
®
C
L
A
100
PD
1200
NA
Part description
Thyristor (SCR)
High Efficiency Thyristor
(up to 1200V)
Phase leg
SOT-227B (minibloc)
=
=
=
Current Rating [A]
Reverse Voltage [V]
=
=
=
=
Package
T
op
°C
M
D
Nm1,5
mounting torque
1,1
T
VJ
°C150
virtual junction temperature
-40
Weight g30
Symbol
Definition
typ.
max.
min.
Conditions
operation temperature
Unit
M
T
Nm1,5
terminal torque
1,1
VV
t = 1 second
V
t = 1 minute
isolation voltage
mm
mm
10,5 3,2
8,6 6,8
d
Spp/App
creepage distance on surface | striking distance through air
d
Spb/Apb
terminal to backside
I
RMS
RMS current
150 A
per terminal
125-40
terminal to terminal
SOT-227B (minibloc)
Similar Part Package Voltage class
CLA60PD1200NA SOT-227B (minibloc) 1200
Delivery Mode Quantity Code No.Ordering Number Marking on ProductOrdering
50/60 Hz, RMS; I ≤ 1 mA
ISOL
CLA100PD1200NA 509048Tube 10CLA100PD1200NAStandard
3000
ISOL
T
stg
°C150
storage temperature
-40
2500
threshold voltage
V0,83
mΩ
V
0 max
R
0 max
slope resistance *
1,8
Equivalent Circuits for Simulation
T =
VJ
I
V
0
R
0
Thyristor
150 °C
* on die level
IXYS reserves the right to change limits, conditions and dimensions. 20150827bData according to IEC 60747and per semiconductor unless otherwise specified
© 2015 IXYS all rights reserved
CLA100PD1200NA
4 3 21
Outlines SOT-227B (minibloc)
IXYS reserves the right to change limits, conditions and dimensions. 20150827bData according to IEC 60747and per semiconductor unless otherwise specified
© 2015 IXYS all rights reserved
CLA100PD1200NA
0,01 0,1 1
500
600
700
800
900
1000
1100
1200
13
0
0
0,5 1,0 1,5
0
50
100
150
2
00
1 10 100 1000 10000
0,0
0,1
0,2
0,3
0,4
I
TSM
[A]
I
T
[
A]
V
T
[V]
t [ms]
Z
thJC
[K/W]
2 3 4 5 6 7 8 9 011
0
4000
8000
1
2
000
I
2
t
[A
2
s]
t [ms]
I
T(AV)M
[A]
T
C
[°C]
0 25 50 75 100 125 150
0
20
40
60
80
100
120
140
160
Fig. 1 Forward characteristics Fig. 3 I
2
t versus time (1-10 ms)
t [s]
Fig. 6 Max. forward current
at case temperature
Fig. 2 Surge overload current
Fig. 8 Transient thermal impedance junction to case
T
VJ
= 25°C
T
VJ
= 125°C
T
VJ
= 45°C
50 Hz, 80% V
RRM
T
VJ
= 125°C
T
VJ
= 45°C
V
R
= 0 V
125°C
150°C
0 20 40 60 80 100 120
0
40
80
120
160
I
T(AV)
[A]
P
(AV)
[W]
Fig. 7a Power dissipation versus direct output current
Fig. 7b and ambient temperature
0 50 100 150
T
amb
[°C]
dc =
1
0.5
0.4
0.33
0.17
0.08
10 100 1000
1
10
100
1000
1 10 100 1000 10000
0,1
1
10
I
G
[mA]
V
G
[V]
4: P
GAV
= 0.5 W
5: P
GM
= 1 W
6: P
GM
= 10 W
t
gd
[µs]
I
G
[mA]
typ. Limit
T
VJ
= 125°C
Fig. 4 Gate trigger characteristics Fig. 5 Gate controlled delay time
6
45
2
1
3
dc =
1
0.5
0.4
0.33
0.17
0.08
1: I
GD
, T
VJ
= 150°C
2: I
GT
, T
VJ
= 25°C
3: I
GT
, T
VJ
= -40°C
R
thHA
0.2
0.4
0.6
0.8
1.0
2.0
R
thi
[K/W] t
i
[s]
0.022 0.011
0.014 0.001
0.083 0.04
0.096 0.40
0.135 0.16
Thyristor
IXYS reserves the right to change limits, conditions and dimensions. 20150827bData according to IEC 60747and per semiconductor unless otherwise specified
© 2015 IXYS all rights reserved
