AK2711 - AKM Semiconductor, Inc.

PRELIMINARY

AK2711

High Speed DAC w/16-Bit Resolution at 1.2 MSPS

Features

• Monolithic 16-Bit Overs am pled DAC

• 16 x Oversampling, 20 MSPS Clock

• Internal low jitter PLL allows clock input

spe eds of 2, 4, 8 and 16 x samp le clock.

• 1.25 M H z I n put Wor d Ra t e

• AC Specifications

• 500 kHz Si g n a l Pa s s b and

• Signal - to-Noise: 86 dB

• Signal-to-(Noise plus Distortion): 82.5 dB

• Dynamic range: 86 dB

• Out-of-band (up to 10 Mhz): 70 dB

• Digital Filter

• Passband Ripple: 0.05dB

• Stopband Attentuation: 70dB

• Low Power Dissipation 200 mW

• Power Su pply

• A nalog Supp ly + 5 V

• D igital Supply + 3 V/ + 5 V

• 4 V Vpp differential glitch free output

• Edge triggered input latch for parallel data

input

• 44 pin LQFP package

The AK2711 is a 16-bi t, high spe ed ove rsampled

digital-to-analo g converter opti mized for waveform

r econstruction applic ations requiring high dynamic

r ange. Glitches that are characteris tic of Nyquis t rate

DACs are avoided by use of an over-sampled, multi-

bit sigma-delta arch itecture. The AK271 1 is

manufac tured on an advanced su bmi cron analog

pr oce ss. High dynamic range is achieved by the use

o f pr opr ietar y multi bit delta sigma technique s.

The AK2711 is a switche d capacitor DAC, with a

nomi nal full scale differ ential out put of 4 V with a

com mon -mode output level of 2 .5V.

The on-chip inte rpolation filter suppresses original

Block Diagram

inb a nd imag es eli m i n at in g th e ne ed for co mp lex

external analog smoothing filters. Additional out-of-

band filtering is provided after the sigma- delta DAC

The on-chip referenc e a nd refe rence buffer amplifier

ar e config ured f or maxi mum accura cy and fl exibi lity.

Phase -Lock-Loo p cloc k mul tiplier provides the

nece ssar y synchroni zed 16fs cloc k to support the

over-sampled DAC. An external synchronous clock

can also be us ed.

The AK271 1 ope rate s on a sin gle +5 V a nalog supply

and +5 V/ +3 V digi tal supply, typically cons uming

200mW. Th e AK2711 is available in a 4 4-lead L QFP

packa ge and is spe cified to operate from -40 to 85C.

DVDD

DVSS

CEN

PLL + MUX

REFERENCE

BUFFER

BANDGAP

REFERENCE

AK2711

INPUT REGISTER

MCLK

RBIAS

BIT1-BIT16

REFP

AVSS

AVDD

AVSS

AVDD

AVSS

VCOM

REFN

MCEN

MCBP

ORDER

CONTINUOUS LPF

OUTP

OUTN

OUTPUT

BUFFER

SCLK

STAGE 3

INTERPOLATION

FILTER

STAGE 2

INTERPOLATION

FILTER

STAGE 1

INTERPOLATION

FILTER

MULTIBIT

SIGMA-DELTA

MODULATOR

DAC

ORDER SWITCHED

CAPACITOR LPF

Description

PRELIMINARY

212/1999

PERFORMANCE SPECIFICATION

DC S PECIFICATION

AVDD = 5.0V, DVDD = 3V, AGND = DGND = 0V, fMCLK = 20 MSPS, TMAX=85C, TMIN=-40C

Parameter Conditions/Comments Min. Typ. Max. Units

Resolution 16 Bits

Accuracy

In tegra l N onlineari ty (INL) +2LSB

Dif ferential N onlin earity (DNL) +0.8 LSB

Monotonici ty Bits G uaranteed 116 Bits

Of fset Er ror No te 1 0.3 TB D % FS R

Gain Error Note 1 TBD -3.5 TBD % FSR

Temperature Drift

Offset Error 1.1 ppm/C

Gain Error 50 ppm/C

Power Supply Rejection

AVDD,DVDD,SVDD 50 mV s upp ly r ipple(5 00kHz) 0.1 % FSR

Anal og O utput

Output Full Scale VREF = 2.5V 4 Vp-p Di ff

Output Co mmon Mo de V oltage 2.43 V

Output Load Resistance 2 k ohms

Output Load Capacitance 20 pF

Internal Voltage Reference

Output Voltage TBD 2.43 TBD V

Power Supplies

AVDD & SVDD 4.75 5 5.25 V

DVDD 2.7 3 5.25 V

Supply Currents

I(AVDD + SVDD) 100kHz Input, -2.2 dBFS135 TBD mA

I(DVDD) 100kHz Input, -2.2dBFS 19TBDmA

Power Consumption

Powe r 100kH z Input, -2.2dBFS1202 mW

PRELIMINARY

ASAHI KASEI AK2711

12/1999 3

AC S PECIFICATION

AVDD = +5V, DVDD= +3V, fMCLK = 20 MSPS, T MAX=85C, TMIN=-40C

Parameter Conditions/Comments Min. Typ. Max. Units

DYNAMIC PERFORMANCE

Input Test Frequency: 100 KHz

Signal to Noise (SNR) Input Amplitude: -0.5dBFS1TDB 86 dB

Input Amplitude: -6 dBFS 80 dB

SNR + Distortion (S INAD) Input Amplitud e: -0.5 dBFS1TBD 82.5 dB

Input Amplitude: -6 dBFS 79 dB

Total Harmonic Distortion (THD) Input Amplitude: -0.5 dBFS185 TDB dB

Input Amplitude: -6 dBFS 88 dB

Spurious Free Dynamic Range (SFDR) Input Amplitude: -0.5 dBFS1TBD 86 dB

Input Amplitude: -6 dBFS 89 dB

Input Test Frequency: 500 KHz

Signal to Noise (SNR) Input Amplitude: -0.5dBFS 86 dB

Input Amplitude: -6 dBFS 80 dB

Spurious Free Dynamic Range (SFDR) Input Amplitude: -0.5 dBFS 86 dB

Input Amplitude: -6 dBFS 89 dB

INTERMODULATION DISTO RTION

fIN1 = 475 kHz, fIN2 = 525 kHz TBD dBFS

DYNAMIC CHARACTERISTICS

Settling Ti me To 0.003% FS TBD us

Output Propagation Delay TBD Clocks

Output Noise Voltage 71 uV rms

DIGITAL FILTER CHARACTERISTI CS

Parameter Conditions/Comments Min. Typ. Max. Units

DAC Filter

Passband Ripple 0 to 0.4 fs ±0. 05 dB

Stopband Attenuation > 0.59 6 fs -70 dB

PERFORMANCE SPECIFICATION[continued]

PRELIMINARY

412/1999

Notes

1. 100% produc tion tested at 25C and samp le tested at the specified tem peratures.

DIGITAL SPECIFICATION

AVDD = +5V, DVDD = +5V, TMAX=85 C, TMIN=-40C

Parameter Conditions/Comments Min. Typ Max Units

VIH High Le vel Inpu t Voltage Clock Pin 2 V

VIL Low Level Input Volt age Clock Pin 0.8 V

VIH Hi gh Level Input Voltage All ot her pins 0.7*DVDD V

VIL Low Level Input Voltage All oth er pins 0.3 *DVDD

RPULLDOWN Pull Down Resistance MCEN, MCBP, R1, R0, M1,

M0, TST, DITHEN,

DEMEN, SCAN

10 50 K Ohms

IIL Input Leakage Current All pins except internal pull-

down pins +10 uA

Absolute Maximum Ratings

AGND, SGND,RGND and DGND = 0V. All voltages are with respect to ground.

Parameter Mi n. Max. Units

Power Supplies

VA Anal og Powe r Supply -0. 3 6.0 V

VD Digi tal Power Supply -0. 3 VA V

GND Difference between AGND, SGND, AGND2 and DGND 0.3 V

IIN Input Current—All pins except supply pins ±10 mA

VIND Di gital Input V o ltage -0.3 VD + 0 .3 V

Temperature

Ta Ambient Operating Tempe rature (Power A pplied) -40 80 °C

Tstg S torage Temperature -65 15 0 °C

Recommended Operation C o nditions

AGND, SGND, AGND2, and DGND = 0V. All voltage s ar e with respect to ground.

Parameter Min. Typ. Max. Units

Power Supplies1

VA Analog Power Supply (AVDD & SVDD) 4.75 5.0 5.25 V

VD Digital Power Supply (DVDD) 2.7 3.3 VA V

PERFORMANCE SPECIFICATION[continued]

PRELIMINARY

ASAHI KASEI AK2711

12/1999 5

PIN LAYOUT

Digital Switching Characteristics

AVDD = +5V, DVDD=5V, CL=20pF, TMAX=85C, TMIN=-40C

Param eter Conditions/Comments Mi n. Typ. Max. Units

tMCLK Master Clock Period 50 ns

tSCLK Sample Clock Period 800 ns

tMCLKH Mas ter Clock Pulse Width High 20 ns

tMCLKL Mas ter Clock Pulse Width Low 20 ns

tSCLKH Sample Clock Pulse Width High 396 ns

tSCLKL Sample Clock Pulse Width Low 396 ns

tS Input Setup Time to SCLK 5 ns

tH I nput Hold Time af ter SCLK 5 n s

D10

SVDD

AVSS

REFH

REFL

RBIAS

AVDD

AVSS

VCOM

OUTP

OUTN

DITHEN

D11

D12

D13

D14

D15

DVDD

DVSS

AVSS

SCAN

TST

DEMEN

SCLK

TCLK

MCEN

MCBP

CEN

MCLK

SVSS

44 LQFP

AK2711

PRELIMINARY

612/1999

PIN DESCIPTION

No. Pin Name I/O Pin Function and Descr iption

1-16 D0-D15 I Data Input. (MSB = Pin 16 LSB = Pin1)

17 DVDD 3V Digital Supply. DVDD = 3/5V

18 DVSS 3V Digital Ground. DVSS = 0V

19 AVSS Analog Ground. AVSS=0V

20 SCAN I Test Mode Pin

21 TST I Test Mode Pin

22 DEMEN I Test Mode Pin

23 DITHEN I Dither Enable (Active low)

24 OUTN O Differential Analog Output

25 OUTP ODifferential Analog Output

26 VCOM O Intern al Common mode voltage

27 AVSS Analog Ground. AVSS=0V

28 AVDD Analog Supply. AVDD = 5V

29 RBIAS I Resistor Connected to Ground (4.99K ohm s)

30 REFL O 1V ou tp ut de rive d from in te rna l b and g ap vol t a ge

31 REFH O 4V ou tp ut de rive d from in te rna l b and g ap vol t a ge

32 AVSS Analog Ground. AVSS=0V

33 SVDD 5 V Analog Supply SVDD = 5V

34 SVSS Analog Ground. SVSS = 0V

35 MCLK I Master Clock

36 CEN I Chip Enable (Activ e H igh)

37 M0 I P L L Mod e Pi n s. M1,M0 00 - M CLK = SCLK ; 01 - M CLK = 2SCLK , 10- MCLK = 4S CLK;

11 - M C LK = 16S CLK .

38 M1 I

39 R0 I Connected to 0V

40 R1 I Connected to 5V

41 MCBP I PLL Bypass

42 MCEN I Enables PLL Clock Output

43 TCLK O PLL Clock Output

44 SCLK I Sa m p le C lock (Data is latched on the positive edge of the clock)

PRELIMINARY

ASAHI KASEI AK2711

12/1999 7

TH EO RY OF OP E RATIO N

The AK2711 is a 16 bit, 2.5MSPS Digital to Analog

converter intended for xDSL and high speed

instrumentation, medical imaging and high resolution,

high spe ed s ignal generation. A novel delta-sig ma

modula tor operating at 20Mhz employing multibi t

quantization and dynamic element ma tching tec hniques

achieves 86dB signal to noise performance, with a 86dB

of spurious free dyna mic range and a low power

dissipation of 200mW.

The on-chip interpolation filter and continuos time filter

provides excellent stop-band rejection to suppress any

stray signal greater than 0.745MH z, substantially easing

the requirements of any anti-imaging filter for the analog

outpu t path.

The AK2711 features an internal digital PLL to provide

flexibility in the cl ock i nput. The PLL MODE pi n allow

for dif f erent cl ocking options . A dig ital suppl y of 5.25 to

2.7V can be us ed, though a 3V supply is recommended to

minimize digit al noise on the board. The CEN pin is

provided to reset the internal filters, in case of an

overflow condition and correct initializa tion during

power up.An on-chip reference and refere nce buffer is

includ ed on th e AK271 1. The 2 .5V reference provide s for

a 4V pk-pk differential output full scale.

Digital Inputs

A paralle l da ta inte rfac e uses the sa mple c lock (S CLK) to

clock in the input data. The posit ive edge of SCLK

strobes the 2’s compl ement dat a into t he in put regis ters of

the AK2711. The SCLK can be asynchronous to the

master clock (MCLK).

Digital Interpolation Filter

The purpose of the interpolator is to oversamp le the input

data, i.e. to increase the sample rate so that the

attentuati on requirements on the analog filte rs are

relaxed. The interpolati on is performed using a multis tage

FIR digital filters.The filtering introduces a +0.05dB of

passband ripple and a stopband attentuation of -70dB.

Multibit Sigma Delta Modulator

The AK2711 employs a mu lti bit sigma delta using

proprietary dynamic element ma tching tec hniques to

provide excellent linearity.

Dither Generator

The AK2711 includes an on chip dither generator, which

is intended to further reduce the quantization noise

introduced by the multibit DAC. This dithering can be

externally turned off using a test mode pin, DITHEN.

Analog Filtering

The AK2711 includes a 3rd order switch ed capacitor

discrete time low pa ss filter followed by a 2nd order

analog continuos time low pass filter. These filters

elim inate the need f or any ad ditional off chip ext ernal

reconstruction filtering. The continuos time filtering

results in glit ch fre e output waveforms.

Phase Lock Loop

A digital phase lock l oop is integrated on chip to provide

flexibility in clocking. The Mode pins allow MCLK to

1x, 2x, 4x and 16x t imes the SCLK fr equenc y. The Range

pins allow for a different ranges of SCLK from 625K Hz

to 2.5MHz. The best performanc e is achieved when the

PLL is bypassed.

Analog Output and Reference Overview

The va lue o f VCM defines the maximum output voltage

to the AK2711. An internal referenc e buffer scal es the

VCM of 2.5V to create REFH and REFL. The scale factor

for thes e buf fers i s 0.8. Thus the maxi mum ou tput vol ta ge

of the D/A is defined to be +0.8 x VCM = +2V to -0.8 x

VCM = -2V.

Output Drive, Buffering and Loading

The A K2711 analo g outpu t s tag e is abl e to dr ive a loa d of

1K ohms. If a singl e end ed output is require d, a

differential to single ended instrument op amp circuit is

required. Level scaling can also be achieved easily using

th is circuit.

DIFFERENTIAL TO SINGLE ENDED DRIVER

Figur e 1: AC Couple d Different ial Buff er with Level Shifting

PRELIMINARY

AK2711 ASAHI KASEI

812/1999

REFERENCE OPERATION

T h e AK 27 11 con tai ns an in t eg r at ed ba n d ga p ref e r en c e

and a i nternal reference buf fer ampl ifier. This reference

genera tes a 2.5V. The actual voltages us ed by the intern al

circui try of the AK2711 appear on the RE FH and REFL

pins. For proper operation, it is necessary to add a

capacitive network to decoup led t he pins. All di gital

switching lines must be drawn away from these pins.

BIAS PIN

The pin is connecte d to a 4.99k ohms. This set s up the

bias currents to all the analog circuitry. Minimization of

capacitance to this pin is recommende d in order to

prevent instability of the bias pin amplifier.

CLOCK INPUT CONSIDERATION

The cl ock input shoul d be treated as an analog signal in

cases where aperture jitter may affect the dynamic range

of the AK2711. The CLK in put buf fer is po wered by a 5V

analog supply and requires high and low levels of 3.5V

and 1V respectively. Low jitter crystal c ontrolled

osci llators make the bes t clock source

GROUNDING AND DECOUPLING

An a l og and Dig ita l Ground in g

Multi layer printed circuit boards (PCBs) are

recommended to provide for optimal grounding and

power schemes. The use of ground and power planes

resul ts in bo th a reduc ti on of electro magne tic i nte rference

(EMI) and an overal l im provement in perf ormance.

It is important to des ign a layout that preve nts nois e from

coupling onto the input signal. Digital signals should not

be run in parallel with input signal tra ces and should be

routed away from th e input circuitry. Wh ile AK27 11

features separat e ana log and digital pins, it should be

treated as an analog component.

Analog and Digital Supply De coupling

The analog and digital suppli es should be decoupled as

clos e to the chi p as physic ally pos sib le . A com binati on of

0.1uF and 10uF sh ould be conne cted between each pair of

power supplies: AVDD and AVSS, DVDD and DVSS,

and SVDD and SVS S. A n external decoupling and bias

network is shown in figure 2.

F igure2: D ecoupling and Bias C onnection for AK2711

DATA

AK2711

DATA

DVDD

DVSS

AVSS

SCAN

TST

DEMEN

SVDD

AVSS

REFH

REFL

RBIAS

AVDD

AVSS

VCOM

OUTP

OUTN

DITHEN

SCLK

TCLK

MCEN

MCBP

CEN

MCLK

SVSS

10uF

0.1uF

10uF

10uF 0.1uF

10uF

0.1uF

10uF

0.1uF

10uF

0.1uF

PRELIMINARY

ASAHI KASEI AK2711

12/1999 9

MARKI NG SPEC

AKM

AK2711

XXXXXXX

JAPAN

Marking Spec

XXXXXXX Date and Production Code

JAPAN Country Of Origin

PRELIMINARY

AK2711 ASAHI KASEI

12/1999

Important Notice

These produ cts and their specifications are subject t o change without notice. Befo re considering any use or a pplication, consult the

Asa hi K asei Mi crosy stems Co., Ltd. (AKM) sales office or authorized distri butor concern ing t heir current status.

AKM a ssumes no liability for infringement of any patent, intellectua l pro perty, or other right in the a pplicatio n or use of any infor m a-

tion contained herein .

Any export of these products, or devices or systems containing them, may require an export license or other official approval under

th e law and regulations of the count ry of ex port pertaining to customs and tariffs, currency exchan ge, or strategic materials.

AKM products are neither intended nor authorized for use as critical component s in any safety, lif e support, or other hazard related

device or sy stem, and A K M assumes no respons ibility relating to any such use, except wi th t he express wri tten consent of the Repre-

sentative Director of AK M. As used here:

a. A hazard related device or system is o ne desi gned or inte nded fo r life suppo rt or ma inte nance of safety or for applications in med-

icine, aerospace, nuclear energy, or other fields, in which its failure to function or perform m ay reasona ble b e expected to r esult in

loss of life or in significant inju ry or damage to person or property.

b. A critical componen t is one who se failure to function o r perform m ay reas onably be expected to result, whether directly or indi-

rectly, in the loss of th e safety or effect ivene ss of t he devi ce or sys tem cont aining it, and w hich must therefore meet very high

standar ds of performance and reliability.

It is th e responsibility of the buyer or distributor of an AKM product who con tributes, disposes o f, o r otherwise places the product

with a t hi rd p arty t o no tify tha t pa rty i n ad vanc e of th e ab ove c ont ent an d con di tions , a nd the bu yer or dis tr ibut or a gre es to assume an y

and all r espon sibility and liab ility for and hold AKM har m less from any and a ll c laims arising from the use of said product in the

absence of such notification.

OUTLINE DIMEN SIONS

Dimensions shown in millimeters

0.1 M

0.370.8

10.0

12.8+ 0.3

10.0

12.8+ 0.3

1.4

0.6+0.2

0~10

0.17

0.1

0.1+0.1

1.4

1.7MAX

44-Lead LQFP