SSRAM Austin Semiconductor, Inc. 256K x 18 SSRAM PIN ASSIGNMENT (Top View) Synchronous Burst SRAM, Flow-Through 100-pin TQFP A6 A7 CE\ CE2 NC NC WEH\ WEL\ CE2\ VCC VSS CLK GW\ BWE\ OE\ ADSC\ ADSP\ ADV\ A8 A9 FEATURES MARKING -8 -9 -10 A10 NC NC VCCQ VSSQ NC DQP1 DQ8 DQ7 VSSQ VCCQ DQ6 DQ5 VSS NC VCC ZZ DQ4 DQ3 VCCQ VSSQ DQ2 DQ1 NC NC VSSQ VCCQ NC NC NC and CE2), burst control inputs (ADSC\, ADSP\, and ADV\), write enables (WEL\, WEH\, and BWE\), and global write (GW\). Asynchronous inputs include the output enable (OE\), burst mode control (MODE), and sleep mode control (ZZ). The data outputs (DQ), enabled by OE\, are also asynchronous. Addresses and chip enables are registered with either address status processor (ADSP\) or address status controller (ADSC\) input pins. Subsequent burst addresses can be internally generated as controlled by the burst advance pin (ADV\). Address, data inputs, and write controls are registered on-chip to initiate self-timed WRITE cycle. WRITE cycles can be one or two bytes wide as controlled by the write control inputs. Individual byte enables allow individual bytes to be written. WEL\ controls DQ1DQ8 and DQP1. WEH\ controls DQ9-DQ16 and DQP2. WEL\ and WEH\ can be active only with BWE\ being LOW. GW\ being LOW causes all bytes to be written. The AS5SS256K18 operates from a +3.3V core power supply and all outputs operate on a +2.5V supply. All inputs and outputs are JEDEC standard JESD8-5 compatible. The device is ideally suited for 486, PentiumTM , 680x0, and PowerPCTM systems and for systems that are benefited from a wide synchronous data bus. DQ No. 1001 For more products and information please visit our web site at www.austinsemiconductor.com GENERAL DESCRIPTION The ASI Synchronous Burst SRAM family employs high-speed, low power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high valued resistors. The AS5SS256K18 SRAM integrates 262,144x18 SRAM cells with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining chip enable (CE\), depth-expansion chip enables (CE2\ AS5SS256K18 Rev. 2.0 7/99 1 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 MODE A5 A4 A3 A2 A1 A0 NC NC VSS VCC NC NC * Timing 8ns/10ns 8.5ns/11ns 10ns/20ns * Packages 100-pin TQFP NC NC NC VCCQ VSSQ NC NC DQ9 DQ10 VSSQ VCCQ DQ11 DQ12 NC VCC NC VSS DQ13 DQ14 VCCQ VSSQ DQ15 DQ16 DQP2 NC VSSQ VCCQ NC NC NC A15 A14 A13 A12 A11 A16 A17 * Fast access times: 8, 8.5, and 10ns * Fast clock speed: 100, 90, and 50 MHz * Provide high performance 2-1-1-1 access rate * Fast OE\ access time: 5 ns * 3.3V -5% and +10% power supply * 2.5V or 3.3V I/O Supply * Clamp diodes to VSSQ at all inputs and outputs * Common data inputs and data outputs * BYTE WRITE ENABLE and GLOBAL WRITE control * Three chip enables for depth expansion and address pipeline * Address, data and control registers * Internally self-timed WRITE CYCLE * Burst control pins (interleaved or linear burst sequence) * Automatic power-down for portable applications * Low profile 100 pin TQFP package * Operating Temperature Ranges: - Military -55oC to +125oC - Industrial -45oC to +85oC OPTIONS AS5SS256K18 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 1 SSRAM Austin Semiconductor, Inc. AS5SS256K18 PIN DESCRIPTIONS TQFP PIN NUMBERS SYMBOL TYPE DESCRIPTION 37, 36, 35, 34, 33, 32, 100, 99, 82, 81, 80, 48, 47, 46, 45, A0-A17 93, 94 WEH\, WEL\ 87 BWE\ InputWrite Enable: This active LOW input gates byte write operations and must Synchronous meet the setup and hold times around the rising edge of CLK. 88 GW\ 89 CLK InputGlobal Write: This active LOW input allows a full 18-bit WRITE to occur Synchronous independent of the BWE\ and WEn\ lines and must meet the setup and hold times around the rising edge of CLK. InputClock: This signal registers the addresses, data, chip enables, write control Synchronous and burst control inputs on its rising edge. All synchronous inputs must meet setup and hold times around the clock's rising edge. 98 CE\ InputChip Enable: This active LOW input is used to enable the device and to Synchronous gate ADSP\. 92 CE2\ InputChip Enable: This active LOW input is used to enable the device. Synchronous 97 CE2 86 OE\ InputChip enable: This active HIGH input is used to enable the device. Synchronous InputOutput Enable: This active LOW asynchronous input enables the data Synchronous output drivers. 83 ADV\ 84 ADSP\ 85 ADSC\ 31 MODE 64 ZZ InputAddresses: These inputs are registered and must meet the setup and hold Synchronous times around the rising edge of CLK. The burst counter generates internal addresses associated with A0 and A1, during burst cycle and wait cycle. InputByte Write Enables: A byte write enable is LOW for a WRITE cycle and Synchronous HIGH for a READ cycle. WEL\ controls DQ1-DQ8 and DQP1. WEH\ controls DQ9-DQ16 and DQP2. Data I/O are high impedance if either of these inputs are LOW, conditioned by BWE\ being LOW. InputSynchronous InputSynchronous Address Advance: This active LOW input is used to control the internal burst counter. A HIGH on this pin generates wait cycle (no address Address Status Processor: This active LOW input, along with CE# being LOW, causes a new external address to be registered and a READ cycle is initiated using the new address. InputAddress Status Controller: This active LOW input causes device to be deSynchronous selected or selected along with new external address to be registered. A READ or WRITE cycle is initiated depending upon write control inputs. InputMode: This input selects the burst sequence. A LOW on this pin selects Static LINEAR BURST. A NC or HIGH on this pin selects INTERLEAVED BURST This active HIGH input puts the device in low power InputSnooze: Asynchronous consumption standby mode. For normal operation, this input has to be either LOW or NC (No Connect). 58, 59, 62, 63, DQ1-DQ16 68,69, 72, 73, 8, 9, 12,13, 18, 19, 22, 23 74, 24 DQP1,DQP2 15, 41,65, 91 VCC Input/ Output Data Inputs/Outputs: Low Byte is DQ1-DQ8. HIgh Byte is DQ9-DQ16. Input data must meet setup and hold times around the rising edge of CLK. Input/ Output Supply Parity Inputs/Outputs: DQP1 is parity bit for DQ1-DQ8 and DQP2 is parity bit for DQ9-DQ16. Power Supply: +3.3V -5% and +10% of CLK. 17, 40, 67, 90 VSS Ground 4, 11, 20, 27, 54,61, 70, 77 VCCQ I/O Supply Output Buffer Supply: +3.3V -5% and +10% 5, 10, 21, 26, 55, 60, 71, 76 VSSQ I/O Ground Output Buffer Ground: GND 1-3, 6, 7, 14, 16,25, 28-30, 38, 39,42, 43, 51-53, 56,57, 66, 75, 78, 79, 95, 96 NC ----- AS5SS256K18 Rev. 2.0 7/99 Ground: GND. No Connect: These signals are not internally connected. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 2 SSRAM AS5SS256K18 Austin Semiconductor, Inc. BURST ADDRESS TABLE (MODE=NC/VCC) First Address (external) A...A00 A...A01 A...A10 A...A11 Second Address Third Address Fourth Address (internal) (internal) (internal) A...A01 A...A10 A...A11 A...A00 A...A11 A...A10 A...A11 A...A00 A...A01 A...A10 A...A01 A...A00 BURST ADDRESS TABLE (MODE=GND) First Address (external) A...A00 A...A01 A...A10 A...A11 Second Address Third Address Fourth Address (internal) (internal) (internal) A...A01 A...A10 A...A11 A...A10 A...A11 A...A00 A...A11 A...A00 A...A01 A...A00 A...A01 A...A10 FUNCTIONAL BLOCK DIAGRAM UPPER BYTE WRITE WEH\ BWE\ D Q CLK LOWER BYTE WRITE D Q CE\ CE2 CE2\ ENABLE D Q Power Down Logic ASDP\ A17-A2 Address Register ADSC\ CLR Binary Counter & Logic ADV A1-A0 MODE Output Buffers Input Register 256K x 9 x 2 SRAM Array ZZ OE\ lo byte write GW\ hi byte write WEL\ DQ1 - DQ16 DQP1 DQP2 NOTE: The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions and timing diagrams for detailed information. AS5SS256K18 Rev. 2.0 7/99 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 3 SSRAM AS5SS256K18 Austin Semiconductor, Inc. TRUTH TABLE ADDRESS USED CE\ CE2\ CE2 Deselected Cycle, Power Down None H X X X Deselected Cycle, Power Down None L X L Deselected Cycle, Power Down None L H Deselected Cycle, Power Down None L Deselected Cycle, Power Down None READ Cycle, Begin Burst ADV\ WRITE\ OE\ CLK DQ L X X X L-H High-Z L X X X X L-H High-Z X L X X X X L-H High-Z X L H L X X X L-H High-Z L H X H L X X X L-H High-Z External L L H L X X X L L-H Q READ Cycle, Begin Burst External L L H L X X X H L-H High-Z WRITE Cycle, Begin Burst External L L H H L X L X L-H D READ Cycle, Begin Burst External L L H H L X H L L-H Q READ Cycle, Begin Burst External L L H H L X H H L-H High-Z READ Cycle, Continue Burst Next X X X H H L H L L-H Q READ Cycle, Continue Burst Next X X X H H H H L-H High-Z READ Cycle, Continue Burst Next H X X X H H L READ Cycle, Continue Burst Next H X X X H H H WRITE Cycle, Continue Burst Next X X X H H L X WRITE Cycle, Continue Burst Next H X X X H L X OPERATION ADSP\ ADSC\ L L L L L READ Cycle, Suspend Burst Current X X X H H H H L READ Cycle, Suspend Burst Current X X X H H H H H READ Cycle, Suspend Burst Current H X X X H H H L READ Cycle, Suspend Burst Current H X X X H H H H WRITE Cycle, Suspend Burst Current X X X H H H L X WRITE Cycle, Suspend Burst Current H X X X H H L X L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H Q High-Z D D Q High-Z Q High-Z D D NOTES: 1. X means "don't care." H means logic HIGH. L means logic LOW. WRITE\ = L means [BWE\ + WEL\*WEH\]*GW\ equals LOW. WRITE\ = H means [BWE\ + WEL\*WEH\]*GW\ equals HIGH. 2. WEL\ enables write to DQ1-DQ8 and DQP1. WEH\ enables write to DQ9-DQ16 and DQP2. 3. All inputs except OE\ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK. 4. Suspending burst generates wait cycle. 5. For a write operation following a read operation, OE\ must be HIGH before the input data required setup time plus High-Z time for OE\ and staying HIGH throughout the input data hold time. 6. This device contains circuitry that will ensure the outputs will be in High-Z during power-up. 7. ADSP\ LOW along with chip being selected always initiates an READ cycle at the L-H edge of CLK. A WRITE cycle can be performed by setting WRITE\ LOW for the CLK L-H edge of the subsequent wait cycle. Refer to WRITE timing diagram for clarification. AS5SS256K18 Rev. 2.0 7/99 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 4 SSRAM AS5SS256K18 Austin Semiconductor, Inc. PARTIAL TRUTH TABLE FOR READ/WRITE FUNCTION READ READ WRITE one byte WRITE all bytes WRITE all bytes GW\ H H H H H BWE\ H L L L X WEH\ X H L L X WEL\ X H H L X ABSOLUTE MAXIMUM RATINGS* *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Voltage on VCC Supply Relative to VSS................-0.5V to +4.6V VIN .....................................................................-0.5V to VCC + 0.5V Storage Temperature (plastic) .............................-55C to +125C Max Junction Temperature...................................................+125C Power Dissipation ..................................................................1.4 W Short Circuit Output Current (per I/O)..............................100mA DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS (-55oC < TA < +125oC and -40oC<TA<+125oC; Vcc = 3.3V -5% and +10% unless otherwise noted) * ! ! $ % $ % * * 01 2 01 78 % # 9 $ 2 &&!! ' (') & &!! + " , !! + - . + " , !! + - . + " , !! + #- - + " , !! + #- - //* % & AS5SS256K18 Rev. 2.0 7/99 2 # " " - # . !! / #- * 3 #*+ ! ""! " ". ". ". ""! " . . . ""! " 4 5 6 ""! " '( # #*+ ,- #0 1 #*+ ,- " ## )( & #$% % Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 5 SSRAM AS5SS256K18 Austin Semiconductor, Inc. ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Note 5) (-55C < TA < +125C; VCC = 3.3V -5% and +10%) ! "#$%% #% & ' "#$%% #% & ' ( ( ( THERMAL CONSIDERATION DESCRIPTION CONDITIONS Thermal Resistance - Junction to Ambient Thermal Resistance - Junction to Case Still air, soldered on 4.25 x 1.125 inch 4 - layer PCB SYM TQFP TYP JA 25 JC 9 UNITS C/W C/W TYPICAL OUTPUT BUFFER CHARACTERISTICS OUTPUT HIGH VOLTAGE VOH (V) -0.5 0 0.8 1.25 1.5 2.3 2.7 2.9 3.4 AS5SS256K18 Rev. 2.0 7/99 PULL-UP CURRENT IOH(mA) Min IOH(mA) Max -38 -105 -38 -105 -38 -105 -26 -83 -20 -70 0 -30 0 -10 0 0 0 0 OUTPUT LOW VOLTAGE VOL (V) -0.5 0 0.4 0.8 1.25 1.6 2.8 3.2 3.4 PULL-DOWN CURRENT IOL(mA) Min IOL(mA) Max 0 0 0 0 10 20 20 40 31 63 40 80 40 80 40 80 40 80 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 6 SSRAM AS5SS256K18 Austin Semiconductor, Inc. CAPACITANCE SYMBOL PARAMETER CI MAXIMUM UNITS NOTES 65 pF 4 98 pF 4 TA = 25 C; f = 1 MHz VCC = 3.3V C0 AC TEST CONDITIONS Input pulse levels Input rise and fall times Input timing reference levels Output reference levels Output load 0V to 2.5V 1.8ns 1.25V 1.25V See Figures 1 and 2 OUTPUT LOADS 3.3v 317 DQ DQ Z 0=50 351 50 5 pF Vt = 1.5V Fig. 1 OUTPUT LOAD EQUIVALENT Fig. 2 OUTPUT LOAD EQUIVALENT NOTES: 1. All voltages referenced to VSS (GND). 2. Overshoot: VIH < +4.5V for t < t KC /2. Undershoot: VIL < -2.0V for t < t KC /2 3. Icc is given with no output current. Icc increases with greater output loading and faster cycle times. 4. This parameter is sampled. 5. Test conditions as specified with the output loading as shown in Fig. 1 unless otherwise noted. 6. Output loading is specified with CL=5pF as in Fig. 2. 7. At any given temperature and voltage condition, t KQHZ is less than t KQLZ and t OEHZ is less than t OELZ. 8. A READ cycle is defined by byte write enables all HIGH or ADSP\ LOW along with chip enables being active for the required setup and hold times. A WRITE cycle is defined by at one byte or all byte WRITE per READ/WRITE TRUTH TABLE. 9. OE\ is a "don't care" when a byte write enable is sampled LOW. 10. This is a synchronous device. All synchronous inputs must meet specified setup and hold time, except for "don't care" as defined in the truth table. 11. AC I/O curves are available upon request. 12. "Device Deselected" means the device is in POWER -DOWN mode as defined in the truth table. "Device Selected" means the device is active. 13. Typical values are measured at 3.3V, 25oC and 20ns cycle time. 14. MODE pin has an internal pull-up and ZZ pin has an internal pull-down. These two pins exhibit an input leakage current of +30 A. 15. Capacitance derating applies to capacitance different from the load capacitance shown in Fig. 1. AS5SS256K18 Rev. 2.0 7/99 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 7 SSRAM AS5SS256K18 Austin Semiconductor, Inc. READ TIMING t KC t KL 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 1234567890123 1234567 1 1234567890123 1234567 1 1234567890123 1234567 1 1234567890123 1234567 1 1234567890123 1234567 1 1234567890123 1234567 1 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 tH 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 12 12 12 12 12 Q(A2+1) 12 Q(A2+2) BURST READ SINGLE READ 12 123 12 123 12 Q(A2+3) 123 Q(A2) Q(A2+2) 123 123 12 Q(A2+1) 123 123 123 Q(A2) 123 123456 123456 123456 123456 123456 123456 123456 t KQ 123 123 123 123456 123456 123456 123456 123456 123456 123456 Q(A1) t OEQ t OELZ 123 123 123 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 t KQ 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 tS KQLZ DQ t 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 OE\ 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 1234567890123456789012345678901212345678901234567890123456789012123456789012345678 1234567890123456789012345678901212345678901234567890123456789012123456789012345678 1234567890123456789012345678901212345678901234567890123456789012123456789012345678 1234567890123456789012345678901212345678901234567890123456789012123456789012345678 1234567890123456789012345678901212345678901234567890123456789012123456789012345678 1234567890123456789012345678901212345678901234567890123456789012123456789012345678 1234567890123456789012345678901212345678901234567890123456789012123456789012345678 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 1234 123456789 12345 1234 123456789 12345 1234 1234 123456789 12345 1234 123456789 12345 1234 1234 1234 123456789 12345 1234 123456789 1234 12345 1234 1234 123456789 12345 1234 1234567890123456789012 1234567 12 1234567890123456789012 1234567 12 1234567890123456789012 1234567 12 1234567 12 1234567890123456789012 1234567 12 ADV\ 1234567890123456789012 1234567890123456789012 1234567 12 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 12345678 12345678901234567890123456789012123456789012345678901234567890121234567890123456789 1 12345678 12345678901234567890123456789012123456789012345678901234567890121234567890123456789 1 12345678 1 12345678901234567890123456789012123456789012345678901234567890121234567890123456789 12345678 1 12345678901234567890123456789012123456789012345678901234567890121234567890123456789 12345678 1 12345678901234567890123456789012123456789012345678901234567890121234567890123456789 12345678 1 12345678901234567890123456789012123456789012345678901234567890121234567890123456789 A2 H 1234567890123456789012 1234567 12 1234567890123456789012 1234567 12 1234567 12 WEH\, WEL\, 1234567890123456789012 1234567890123456789012 1234567 12 1234567890123456789012 1234567 12 1234567890123456789012 1234567 12 BWE\, GW\ 123456 123456789012 1 123456 123456789012 1 123456 123456789012 1 123456 123456789012 1 123456 123456789012 1 123456 123456789012 1 123456 123456789012 1 123456 123456 123456 123456 123456 123456 12345678 1234 12345678 12345678 1234 12345678 12345678 12345678 1234 12345678 12345678 1234 12345678 12345678 1234 12345678 12345678 1234 A1 t 123456 123456 123456 123456 123456 123456 t S 1234567 1234567 12 1234567 1234567 12 1234567 12 1234567 1234567 12 1234567 ADDRESS 1234567 1234567 12 1234567 12 1234567 CE\ (See Note) 123456 123456 123456 123456 123456 123456 123456 H 12345 123456789 1234 12345 123456789 1234 12345 123456789 1234 12345 1234 123456789 12345 1234 123456789 12345 123456789 1234 t KH 123456 123456 123456 123456 123456 123456 123456 1234 1234 1234 ADSC\ 1234 1234 1234 t 1234567 1234567 1234567 1234567 1234567 1234567 1234567 123456 123456 123456 123456 123456 123456 t S 123456 1234 1234 1234 1234 ADSP\ 1234 1234 1234 CLK NOTE: CE\ active in this timing diagram means that all chip enables CE\, CE2, and CE2\ t are active. AS5SS256K18 Rev. 2.0 7/99 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 8 SSRAM AS5SS256K18 Austin Semiconductor, Inc. WRITE TIMING 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 1234 123456789 12345 1234 1234 123456789 12345 1234 123456789 1234 12345 1234 1234 123456789 12345 1234 123456789 1234 12345 1234 1234 123456789 12345 1234 123456 1234567890123456789012 1 123456 1234567890123456789012 1 123456 1234567890123456789012 1 123456 1 1234567890123456789012 123456 1234567890123456789012 1 123456 1234567890123456789012 1 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 12345678 123456789012345678 12 12345678 123456789012345678 12 123456789012345678 12345678 12 12345678 12 123456789012345678 12345678 123456789012345678 12 12345678 123456789012345678 12 tH 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 A3 1234567 1234567 1234567 1234567 1234567 1234567 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 12 12 12 12 12 12 D(A3+1) 12 12 D(A3+2) D(A3) 123 123 12 12 D(A2+2) 12 12 D(A2+2) 12 12 D(A2+3) 123 123 BURST WRITE 12 12 SINGLE WRITE D(A2+2) D(A2) 123456 123456 123456 123456 123456 123456 123456 tS 123456 123456 123456 123456 123456 123456 1234 12345 12 1234 12 12345 12345 12345 12345 12345 12345 12345 123456789012 123456789012345678901234567890121234567890123456789012345678901212345678901234567 1 123456789012 123456789012345678901234567890121234567890123456789012345678901212345678901234567 1 123456789012 123456789012345678901234567890121234567890123456789012345678901212345678901234567 1 123456789012 123456789012345678901234567890121234567890123456789012345678901212345678901234567 1 123456789012 123456789012345678901234567890121234567890123456789012345678901212345678901234567 1 123456789012 123456789012345678901234567890121234567890123456789012345678901212345678901234567 1 1234 12345 12 1234 12 12 12 12345 D(A1) 1234 1234 12345 12 1234 1234 12 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 12345 12345 12345 12345 12 12345 12345 12 12345 12345 12 123456 123456 123456 123456 123456 123456 123456 123456 Q KQX t 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 12345 1234 12345678901234567890123456789012123456789012345678901 1234 1234 12345 12345678901234567890123456789012123456789012345678901 1234 1234 12345 12345678901234567890123456789012123456789012345678901 1234 1234 12345 1234 12345678901234567890123456789012123456789012345678901 1234 12345 12345678901234567890123456789012123456789012345678901 1234 1234 12345 12345678901234567890123456789012123456789012345678901 1234 12345 123456789 12345 12345 123456789 12345 123456789 12345 12345 12345 123456789 12345 123456789 12345 12345 12345 123456789 12345 t OEHZ DQ 123456 123456 123456 123456 123456 123456 123456 OE\ 123456 123456 123456 123456 123456 123456 123456 123456 1234 1234567890 12345 1234 1234 1234567890 12345 1234 1234 1234567890 12345 1234 1234 12345 1234 1234567890 1234 1234567890 12345 1234 1234 1234567890 12345 1234 12345 1234 123456789 12345 12345 1234 123456789 12345 12345 1234 123456789 12345 12345 1234 12345 123456789 12345 1234 123456789 12345 12345 1234 123456789 12345 123456789012345678 123456789012345678 123456789012345678 123456789012345678 123456789012345678 123456789012345678 123456 123456 123456 123456 123456 123456 123456 123456 12345 123456789 12345 12345 123456789 12345 12345 12345 123456789 12345 12345 123456789 12345 12345 123456789 12345 12345 123456789 12345 123456789 12345 1234 1234 1234 ADV\ 1234 1234 1234 123456 123456 123456 123456 123456 123456 123456 1234567 1234567890123456789012345678901212345678901234 1 12345678 12 1234567 1234567890123456789012345678901212345678901234 1 12345678 12 1234567890123456789012345678901212345678901234 1234567 1 12345678 12 1234567 1 12345678 12 1234567890123456789012345678901212345678901234 1234567 1234567890123456789012345678901212345678901234 1 12345678 12 1234567 1234567890123456789012345678901212345678901234 1 12345678 12 12345 123456789 12345 12345 123456789 12345 12345 123456789 12345 12345 12345 123456789 12345 123456789 12345 12345 123456789 12345 12345 12345 12345 12345 12345 12345 12345 A2 123456 1234567890123 1 123456 1234567890123 1 123456 1234567890123 1 CE\ 123456 1234567890123 1 123456 1234567890123 1 1234567890123 1 (See Note) 123456 H 12345678901234567 12345678901234567 12345678901234567 12345678901234567 12345678901234567 12345678901234567 12345 123456789 1234 12345 123456789 1234 12345 1234 123456789 12345 1234 123456789 12345 1234 123456789 12345 1234 123456789 12345 123456789 1234 1234 1234 1234 1234 GW\ 1234 1234 1234 1234 WEH\, WEL\, 1234 1234 1234 BWE\ 1234 t 12345 123456789 12345 12345 123456789 12345 12345 123456789 12345 12345 12345 123456789 12345 12345 123456789 12345 12345 123456789 12345 12345 12345678 123 12345678 12345678 123 12345678 123 12345678 12345678 12345678 12345678 123 12345678 123 12345678 12345678 123 12345678 A1 t S 1234567 1234567 12 1234567 1234567 12 1234567 1234567 12 1234567 12 ADDRESS 1234567 1234567 1234567 12 1234567 1234567 12 123456 123456 123456 123456 123456 123456 H 123456 123456 123456 123456 123456 123456 t 12345 1234 123456789 1234 1234 12345 123456789 1234 1234 12345 123456789 1234 1234 12345 1234 123456789 1234 12345 1234 123456789 1234 12345 1234 123456789 12345 1234 1234 1234 1234 ADSC\ 1234 1234 1234 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 t S 1234 1234 1234 ADSP\ 1234 1234 1234 CLK BURST WRITE NOTE: CE\ active in this timing diagram means that all chip enables CE\, CE2, and CE2\ are active. AS5SS256K18 Rev. 2.0 7/99 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 9 SSRAM AS5SS256K18 Austin Semiconductor, Inc. READ/WRITE TIMING 123456 123456 123456 123456 123456 123456 123456 D(A5) 123 D(A5+1) 123 123 123456 123456 123456 123456 123456 123456 123456 1234567 123456789012 1234567 123456789012 12 1234567 123456789012 12 1234567 123456789012 12 1234567 123456789012 12 1234567 123456789012 12 1234567 123456789012 12 123456 123456 123456 123456 123456 123456 123456 1234 123456789012345678901 12345 1234 1234 123456789012345678901 12345 1234 1234 123456789012345678901 12345 1234 1234 12345 1234 123456789012345678901 1234 123456789012345678901 12345 1234 1234 123456789012345678901 12345 1234 BURST WRITE 12345678 12345678 12 12345678 12345678 12 12345678 12345678 12 12345678 12 12345678 12345678 12345678 12 12345678 12345678 12 123456 123456 123456 123456 123456 123456 BURST READ A5 123456 123456 123456 123456 123456 123456 12 123 12 1 Q(A4+2) 12 12 12 Q(A4+1) 123 123 12 Q(A4+3) SINGLE WRITE Q(A4) 12 12 12 SINGLE READS 12 12 12 D(A3) 1234 1234 1234 1234 Q(A1) 1234 1234 Q(A2) 12345678 12345678901234567890123456789012123 1 12345678 1 12345678 12345678901234567890123456789012123 1 12345678 1 12345678901234567890123456789012123 12345678 1 12345678 1 12345678 1 12345678 1 12345678901234567890123456789012123 12345678 12345678901234567890123456789012123 1 12345678 1 12345678 12345678901234567890123456789012123 1 12345678 1 123456789012345678 123456789012345678 123456789012345678 123456789012345678 123456789012345678 123456789012345678 DQ 123456 123456 123456 123456 123456 123456 12345 123456789012345678901234567890121234567890123456789012345678901 12345 12345 123456789012345678901234567890121234567890123456789012345678901 12345 1234 12345 12345 123456789012345678901234567890121234567890123456789012345678901 1234 12345 12345 123456789012345678901234567890121234567890123456789012345678901 1234 12345 12345 123456789012345678901234567890121234567890123456789012345678901 1234 12345 12345 123456789012345678901234567890121234567890123456789012345678901 1234 12345 123456789012345678901234567890121234567890123456789012345678901 12345 1234 OE\ A4 123456789012345 123456789012345 123456789012345 123456789012345 123456789012345 123456789012345 12345 1234567890 1234 12345 1234567890 1234 1234 12345 1234 1234 1234567890 12345 1234 1234567890 1234 12345 1234 1234567890 1234 12345 1234 1234 1234567890 12345 1234567890 1234 1234 12345678901234567890123456789012123456789012 123456 1 12345678901234567890123456789012123456789012 123456 1 12345678901234567890123456789012123456789012 123456 1 123456 1 12345678901234567890123456789012123456789012 123456 1 ADV\ 12345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012 123456 1 1234567890123456 1234567890123456 1234567890123456 1234567890123456 1234567890123456 1234567890123456 A3 H 1234567890123456789012 123456 1 1234567890123456789012 123456 1 12345678 123 1234567 12345678 123 1234567 123 12345678 1234567 12345678 1234567 123 12345678 123 1234567 12345678 123 1234567 t 123456 1 WEH\, WEL\, 1234567890123456789012 1234567890123456789012 123456 1 1234567890123456789012 123456 1 123456 1 BWE\, GW\ 1234567890123456789012 123456 123456789012 12 123456 123456789012 12 12345678 12345678 123 12345678 12345678 123 123 12345678 12345678 12345678 12345678 123 12345678 123 12345678 12345678 123 12345678 A2 123456789012 12 CE\ 123456 123456789012 12 123456 123456789012 12 123456 123456789012 12 123456 (See Note) 123456 123456789012 12 H A1 ADDRESS t t S 12345 12345 12345 ADSC\ 12345 12345 12345 12345 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 t S 1234 1234 1234 ADSP\ 1234 1234 1234 CLK NOTE: CE\ active in this timing diagram means that all chip enables CE\, CE2, and CE2\ are active. AS5SS256K18 Rev. 2.0 7/99 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 10 SSRAM AS5SS256K18 Austin Semiconductor, Inc. MECHANICAL DEFINITIONS ASI Case #1001 (Package Designator DQ) 16.00 + 0.10 14.00 + 0.10 22.00 + 0.10 20.00 + 0.10 1.40 + 0.05 1.60 Max NOTE: All dimensions in Millimeters. AS5SS256K18 Rev. 2.0 7/99 0.65 Basic 0.30 + 0.08 0.60 + 0.15 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 11 SSRAM AS5SS256K18 Austin Semiconductor, Inc. ORDERING INFORMATION EXAMPLE: AS5SS256K18DQ-8/IT Device Number AS5SS256K18 AS5SS256K18 AS5SS256K18 Package Speed ns Process Type DQ -8 /* DQ -9 /* DQ -10 /* *AVAILABLE PROCESSES IT = Industrial Temperature Range XT = Extended Temperature Range AS5SS256K18 Rev. 2.0 7/99 -40oC to +85oC -55oC to +125oC Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 12