AS5SS256K18DQ-8/XT - Micross Components, Inc.

AS5SS256K18

Rev. 2.0 7/99

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

1

SSRAM

AS5SS256K18

Austin Semiconductor, Inc.

FEATURES

• Fast access times: 8, 8.5, and 10ns

• Fast clock speed: 100, 90, and 50 MHz

• Provide high performance 2-1-1-1 access rate

• Fast OE\ access time: 5 ns

• 3.3V -5% and +10% power supply

• 2.5V or 3.3V I/O Supply

• Clamp diodes to VSSQ at all inputs and outputs

• Common data inputs and data outputs

• BYTE WRITE ENABLE and GLOBAL WRITE control

• Three chip enables for depth expansion and address

pipeline

• Address, data and control registers

• Internally self-timed WRITE CYCLE

• Burst control pins (interleaved or linear burst sequence)

• Automatic power-down for portable applications

• Low profile 100 pin TQFP package

• Operating T emperature Ranges:

- Military -55oC to +125oC

- Industrial -45oC to +85oC

OPTIONS MARKING

• Timing

8ns/10ns -8

8.5ns/11ns -9

10ns/20ns -10

• Packages

100-pin TQFP DQ No. 1001

256K x 18 SSRAM

Synchronous Burst SRAM,

Flow-Through

PIN ASSIGNMENT

(Top View)

100-pin TQFP

For more products and information

please visit our web site at

www.austinsemiconductor.com

A6

A7

CE\

CE2

NC

WEH\

WEL\

CE2\

VCC

VSS

CLK

GW\

BWE\

OE\

ADSC\

ADSP\

ADV\

A8

A9

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

NC

VCCQ

VSSQ

NC

DQ9

DQ10

VSSQ

VCCQ

DQ11

DQ12

NC

VCC

NC

VSS

DQ13

DQ14

VCCQ

VSSQ

DQ15

DQ16

DQP2

NC

VSSQ

VCCQ

NC

A10

NC

VCCQ

VSSQ

NC

DQP1

DQ8

DQ7

VSSQ

VCCQ

DQ6

DQ5

VSS

NC

VCC

ZZ

DQ4

DQ3

VCCQ

VSSQ

DQ2

DQ1

NC

VSSQ

VCCQ

NC

MODE

A5

A4

A3

A2

A1

A0

NC

VSS

VCC

NC

A15

A14

A13

A12

A11

A16

A17

GENERAL DESCRIPTION

The ASI Synchronous Burst SRAM family employs high-speed,

low power CMOS designs using advanced triple-layer polysilicon,

double-layer metal technology. Each memory cell consists of four

transistors and two high valued resistors.

The AS5SS256K18 SRAM integrates 262,144x18 SRAM cells

with advanced synchronous peripheral circuitry and a 2-bit counter

for internal burst operation. All synchronous inputs are gated by

registers controlled by a positive-edge-triggered clock input (CLK).

The synchronous inputs include all addresses, all data inputs, ad-

dress-pipelining chip enable (CE\), depth-expansion chip enables (CE2\

and CE2), burst control inputs (ADSC\, ADSP\, and ADV\), write

enables (WEL\, WEH\, and BWE\), and global write (GW\).

Asynchronous inputs include the output enable (OE\), burst mode

control (MODE), and sleep mode control (ZZ). The data outputs

(DQ), enabled by OE\, are also asynchronous.

Addresses and chip enables are registered with either address status

processor (ADSP\) or address status controller (ADSC\) input pins.

Subsequent burst addresses can be internally generated as controlled

by the burst advance pin (ADV\).

Address, data inputs, and write controls are registered on-chip to

initiate self-timed WRITE cycle. WRITE cycles can be one or two

bytes wide as controlled by the write control inputs. Individual byte

enables allow individual bytes to be written. WEL\ controls DQ1-

DQ8 and DQP1. WEH\ controls DQ9-DQ16 and DQP2. WEL\ and

WEH\ can be active only with BWE\ being LOW. GW\ being LOW

causes all bytes to be written.

The AS5SS256K18 operates from a +3.3V core power supply and

all outputs operate on a +2.5V supply. All inputs and outputs are

JEDEC standard JESD8-5 compatible. The device is ideally suited for

486, PentiumTM , 680x0, and PowerPCTM systems and for systems

that are benefited from a wide synchronous data bus.

AS5SS256K18

Rev. 2.0 7/99

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

2

SSRAM

AS5SS256K18

Austin Semiconductor, Inc.

PIN DESCRIPTIONS

TQFP PIN

NUMBERS SYMBOL TYPE DESCRIPTION

37, 36, 35, 34, 33,

32, 100, 99, 82, 81,

80, 48, 47, 46, 45,

A0-A17 Input-

Synchronous Addresses: These inputs are registered and must meet the setup and hold

times around the rising edge of CLK. The burst counter generates internal

addresses associated with A0 and A1, during burst cycle and wait cycle.

93, 94 WEH\, WEL\ Input-

Synchronous Byte Write Enables: A byte write enable is LOW for a WRITE cycle and

HIGH for a READ cycle. WEL\ controls DQ1-DQ8 and DQP1. WEH\

controls DQ9-DQ16 and DQP2. Data I/O are high impedance if either of

these inputs are LOW, conditioned by BWE\ being LOW.

87 BWE\ Input-

Synchronous Write Enable: This active LOW input gates byte write operations and must

meet the setup and hold times around the rising edge of CLK.

88 GW\ Input-

Synchronous Global Write: This active LOW input allows a full 18-bit WRITE to occur

independent of the BWE\ and WEn\ lines and must meet the setup and

hold times around the rising edge of CLK.

89 CLK Input-

Synchronous Clock: This signal registers the addresses, data, chip enables, write control

and burst control inputs on its rising edge. All synchronous inputs must

meet setup and hold times around the clock’s rising edge.

98 CE\ Input-

Synchronous Chip Enable: This active LOW input is used to enable the device and to

gate ADSP\.

92 CE2\ Input-

Synchronous Chip Enable: This active LOW input is used to enable the device.

97 CE2 Input-

Synchronous Chip enable: This active HIGH input is used to enable the device.

86 OE\ Input-

Synchronous Output Enable: This active LOW asynchronous input enables the data

output drivers.

83 ADV\ Input-

Synchronous Address Advance: This active LOW input is used to control the internal

burst counter. A HIGH on this pin generates wait cycle (no address

84 ADSP\ Input-

Synchronous Address Status Processor: This active LOW input, along with CE# being

LOW, causes a new external address to be registered and a READ cycle is

initiated using the new address.

85 ADSC\ Input-

Synchronous Address Status Controller: This active LOW input causes device to be de-

selected or selected along with new external address to be registered. A

READ or WRITE cycle is initiated depending upon write control inputs.

31 MODE Input-

Static Mode: This input selects the burst sequence. A LOW on this pin selects

LINEAR BURST. A NC or HIGH on this pin selects INTERLEAVED

BURST

64 ZZ Input-

Asynchronous Snooze: This active HIGH input puts the device in low power

consumption standby mode. For normal operation, this input has to be

either LOW or NC (No Connect).

58, 59, 62, 63,

68,69, 72, 73, 8, 9,

12,13, 18, 19, 22, 23

DQ1-DQ16 Input/

Output Data Inputs/Outputs: Low Byte is DQ1-DQ8. HIgh Byte is DQ9-DQ16. Input

data must meet setup and hold times around the rising edge of CLK.

74, 24 DQP1,DQP2 Input/

Output Parity Inputs/Outputs: DQP1 is parity bit for DQ1-DQ8 and DQP2 is parity

bit for DQ9-DQ16.

15, 41,65, 91 VCC Supply Power Supply: +3.3V -5% and +10% of CLK.

17, 40, 67, 90 VSS Ground Ground: GND.

4, 11, 20, 27, 54,61,

70, 77 VCCQ I/O Supply Output Buffer Supply: +3.3V -5% and +10%

5, 10, 21, 26, 55,

60, 71, 76 VSSQ I/O Ground Output Buffer Ground: GND

1-3, 6, 7, 14, 16,25,

28-30, 38, 39,42, 43,

51-53, 56,57, 66, 75,

78, 79, 95, 96

NC ----- No Connect: These signals are not internally connected.

AS5SS256K18

Rev. 2.0 7/99

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

3

SSRAM

AS5SS256K18

Austin Semiconductor, Inc.

BURST ADDRESS T ABLE (MODE=NC/VCC)

BURST ADDRESS T ABLE (MODE=GND)

First Address

(external) Second Address

(internal) Third Address

(internal) Fourth Address

(internal)

A...A00 A...A01 A...A10 A...A11

A...A01 A...A00 A...A11 A...A10

A...A10 A...A11 A...A00 A...A01

A...A11 A...A10 A...A01 A...A00

First Address

(external) Second Address

(internal) Third Address

(internal) Fourth Address

(internal)

A...A00 A...A01 A...A10 A...A11

A...A01 A...A10 A...A11 A...A00

A...A10 A...A11 A...A00 A...A01

A...A11 A...A00 A...A01 A...A10

WEH\

BWE\

CLK

WEL\

GW\

CE\

CE2

CE2\

ZZ

OE\

ASDP\

A17-A2

ADSC\

ADV

A1-A0

MODE

D Q

Power Down Logic

D Q

Input

Register

Output Buffers

Address

Register

256K x 9 x 2

SRAM Array

Binary

Counter

& Logic

CLR

UPPER BYTE

WRITE

LOWER BYTE

WRITE

ENABLE

DQ1 - DQ16

DQP1

DQP2

lo byte write

hi byte write

FUNCTIONAL BLOCK DIAGRAM

NOTE: The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions and timing

diagrams for detailed information.

AS5SS256K18

Rev. 2.0 7/99

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

4

SSRAM

AS5SS256K18

Austin Semiconductor, Inc.

TRUTH TABLE

NOTES: 1. X means “don’t care.” H means logic HIGH. L means logic LOW. WRITE\ = L means [BWE\ +

WEL\*WEH\]*GW\ equals LOW. WRITE\ = H means [BWE\ + WEL\*WEH\]*GW\ equals HIGH.

2. WEL\ enables write to DQ1-DQ8 and DQP1. WEH\ enables write to DQ9-DQ16 and DQP2.

3. All inputs except OE\ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.

4. Suspending burst generates wait cycle.

5. For a write operation following a read operation, OE\ must be HIGH before the input data required setup time

plus High-Z time for OE\ and staying HIGH throughout the input data hold time.

6. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.

7. ADSP\ LOW along with chip being selected always initiates an READ cycle at the L-H edge of CLK. A WRITE

cycle can be performed by setting WRITE\ LOW for the CLK L-H edge of the subsequent wait cycle. Refer to

WRITE timing diagram for clarification.

OPERATION ADDRESS

USED CE\ CE2\ CE2 ADSP\ ADSC\ ADV\ WRITE\ OE\ CLK DQ

Deselected Cycle, Power Down None H X X X L X X X L-H High-Z

Deselected Cycle, Power Down None L X L L X X X X L-H High-Z

Deselected Cycle, Power Down None L H X L X X X X L-H High-Z

Deselected Cycle, Power Down None L X L H L X X X L-H High-Z

Deselected Cycle, Power Down None L H X H L X X X L-H High-Z

READ Cycle, Begin Burst External L L H L X X X L L-H Q

READ Cycle, Begin Burst External L L H L X X X H L-H High-Z

WRITE Cycle, Begin Burst External L L H H L X L X L-H D

READ Cycle, Begin Burst External L L H H L X H L L-H Q

READ Cycle, Begin Burst External L L H H L X H H L-H High-Z

READ Cycle, Continue Burst Next X X X H H L H L L-H Q

READ Cycle, Continue Burst Next XXXHH LHH

L-H High-Z

READ Cycle, Continue Burst Next HXXXH LHL

L-H Q

READ Cycle, Continue Burst Next HXXXH LHH

L-H High-Z

WRITE Cycle, Continue Burst Next XXXHH LLX

L-H D

WRITE Cycle, Continue Burst Next HXXXH LLX

L-H D

READ Cycle, Suspend Burst Current X X X H H H H L L-H Q

READ Cycle, Suspend Burst Current X X X H H H H H L-H High-Z

READ Cycle, Suspend Burst Current H X X X H H H L L-H Q

READ Cycle, Suspend Burst Current H X X X H H H H L-H High-Z

WRITE Cycle, Suspend Burst Current X X X H H H L X L-H D

WRITE Cycle, Suspend Burst Current H X X X H H L X L-H D

AS5SS256K18

Rev. 2.0 7/99

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

5

SSRAM

AS5SS256K18

Austin Semiconductor, Inc.

ABSOLUTE MAXIMUM RATINGS*

Voltage on VCC Supply Relative to VSS................-0.5V to +4.6V

VIN .....................................................................-0.5V to VCC + 0.5V

Storage T emperature (plastic) .............................-55°C to +125°C

Max Junction T emperature...................................................+125°C

Power Dissipation ..................................................................1.4 W

Short Circuit Output Current (per I/O)…...........................100mA

*Stresses greater than those listed under "Absolute Maximum

Ratings" may cause permanent damage to the device. This is

a stress rating only and functional operation of the device at

these or any other conditions above those indicated in the

operational sections of this specification is not implied. Expo-

sure to absolute maximum rating conditions for extended peri-

ods may affect reliability .

DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS

(-55oC < TA < +125oC and -40oC<TA<+125oC; Vcc = 3.3V -5% and +10% unless otherwise noted)

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PARTIAL TRUTH TABLE FOR READ/WRITE

FUNCTION GW\ BWE\ WEH\ WEL\

READ H H X X

READ H L H H

WRITE one byte H L L H

WRITE all bytes H L L L

WRITE all bytes H X X X

AS5SS256K18

Rev. 2.0 7/99

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

6

SSRAM

AS5SS256K18

Austin Semiconductor, Inc.

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS

(Note 5) (-55°C < TA < +125°C; VCC = 3.3V -5% and +10%)

THERMAL CONSIDERATION

TYPICAL OUTPUT BUFFER CHARACTERISTICS

OUTPUT HIGH

VOLTAGE OUTPUT LOW

VOLTAGE

VOH (V) IOH(mA) Min IOH(mA) Max VOL (V) IOL(mA) Min IOL(mA) Max

-0.5 -38 -105 -0.5 0 0

0 -38 -105 0 0 0

0.8 -38 -105 0.4 10 20

1.25 -26 -83 0.8 20 40

1.5 -20 -70 1.25 31 63

2.3 0 -30 1.6 40 80

2.7 0 -10 2.8 40 80

2.9 0 0 3.2 40 80

3.4 0 0 3.4 40 80

PULL-UP CURRENT PULL-DOWN CURRENT

DESCRIPTION CONDITIONS SYM TQFP TYP UNITS

Thermal Resistance - Junction to Ambient ΘJA 25 ΟC/W

Thermal Resistance - Junction to Case ΘJC 9ΟC/W

Still air, soldered on 4.25 x

1.125 inch 4 - layer PCB

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AS5SS256K18

Rev. 2.0 7/99

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

7

SSRAM

AS5SS256K18

Austin Semiconductor, Inc.

NOTES:

1. All voltages referenced to VSS (GND).

2. Overshoot: VIH < +4.5V for t < t KC /2.

Undershoot: VIL < -2.0V for t < t KC /2

3. Icc is given with no output current. Icc increases with greater output loading and faster cycle times.

4. This parameter is sampled.

5. Test conditions as specified with the output loading as shown in Fig. 1 unless otherwise noted.

6. Output loading is specified with CL=5pF as in Fig. 2.

7. At any given temperature and voltage condition, t KQHZ is less than t KQLZ and t OEHZ is less than t OELZ.

8. A READ cycle is defined by byte write enables all HIGH or ADSP\ LOW along with chip enables being active for the

required setup and hold times. A WRITE cycle is defined by at one byte or all byte WRITE per READ/WRITE TRUTH

TABLE.

9. OE\ is a “don’t care” when a byte write enable is sampled LOW.

10. This is a synchronous device. All synchronous inputs must meet specified setup and hold time, except for “don’t care” as

defined in the truth table.

11. AC I/O curves are available upon request.

12. “Device Deselected” means the device is in POWER -DOWN mode as defined in the truth table. “Device Selected” means

the device is active.

13. Typical values are measured at 3.3V, 25oC and 20ns cycle time.

14. MODE pin has an internal pull-up and ZZ pin has an internal pull-down. These two pins exhibit an input leakage current

of +30 µA.

15. Capacitance derating applies to capacitance different from the load capacitance shown in Fig. 1.

A C TEST CONDITIONS

OUTPUT LOADS

Input pulse levels 0V to 2.5V

Input rise and fall times 1.8ns

Input timing reference levels 1.25V

Output reference levels 1.25V

Output load See Figures 1 and 2

3.3v

DQ

Fig. 2 OUTPUT LOAD EQUIVALENT

351Ω5 pF

317Ω

Fig. 1 OUTPUT LOAD EQUIVALENT

DQ

50Ω

Z0=50Ω

Vt = 1.5V

CAPACITANCE

SYMBOL PARAMETER MAXIMUM UNITS NOTES

C

I

5pF 4

C

0

8pF 4

T

A

= 25

ο

C; f = 1 MHz

VCC = 3.3V

6

9

AS5SS256K18

Rev. 2.0 7/99

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

8

SSRAM

AS5SS256K18

Austin Semiconductor, Inc.

NOTE: CE\ active in this timing diagram means that all chip enables CE\, CE2, and CE2\ t are active.

123456789012

12345

1234

123456789

1

2345678

9

1

2345678

9

1

2345678

9

1

2345678

9

123456789

12345

1234

READ TIMING

123456

1234

123456789

1

2345678

9

1

2345678

9

1

2345678

9

1

2345678

9

1

2345678

9

123456789

12345

1234

123456

1

2345

6

1

2345

6

1

2345

6

1

2345

6

1

2345

6

123456

1

CLK

ADSP\

S

ADSC\

○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○

ADDRESS A2

WEH\, WEL\,

BWE\, GW\

○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○

CE\

(See Note)

ADV\

OE\

tH

tS

tH

tKQLZ tOELZ

SINGLE READ BURST READ

○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○

DQ

t

1234

A1

12345678

1234

1

23

4

1

23

4

1

23

4

1

23

4

1234

12345678

12345678901234567890123456789012123456789012345678901234567890121234567890123456789

1

234567890123456789012345678901212345678901234567890123456789012123456789012345678

9

1

234567890123456789012345678901212345678901234567890123456789012123456789012345678

9

1

234567890123456789012345678901212345678901234567890123456789012123456789012345678

9

1

234567890123456789012345678901212345678901234567890123456789012123456789012345678

9

12345678901234567890123456789012123456789012345678901234567890121234567890123456789

1

S

tH

t

Q(A2) Q(A2+2)

12

123

12

Q(A2+3)

123

Q(A2)

12

Q(A2+1)

12

Q(A2+2)

1234567

123456

1234

123456

1234567

1

23456

7

1

23456

7

1

23456

7

1

23456

7

1234567

12

123456

Q(A1) Q(A2+1)

123456

tKCtKL

123456

1234567

1234567890123456789012

1

23456789012345678901

2

1

23456789012345678901

2

1

23456789012345678901

2

1

23456789012345678901

2

1234567890123456789012

12

123456

1234567890123456789012345678901212345678901234567890123456789012123456789012345678

1234567

1234567890123456789012

1

23456789012345678901

2

1

23456789012345678901

2

1

23456789012345678901

2

1

23456789012345678901

2

1234567890123456789012

12

1234567890123

1234567

1

23456

7

1

23456

7

1

23456

7

1

23456

7

1234567

1

123

tKH

tKQ tOEQ tKQ

AS5SS256K18

Rev. 2.0 7/99

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

9

SSRAM

AS5SS256K18

Austin Semiconductor, Inc.

NOTE: CE\ active in this timing diagram means that all chip enables CE\, CE2, and CE2\ are active.

WRITE TIMING

1234

123456789

1

2345678

9

1

2345678

9

1

2345678

9

1

2345678

9

123456789

12345

1234

123456

12345

123456789

1

2345678

9

1

2345678

9

1

2345678

9

1

2345678

9

123456789

12345

123456789

1

2345678

9

1

2345678

9

1

2345678

9

1

2345678

9

123456789

12345

1234

1234567890123

123456

1

2345

6

1

2345

6

1

2345

6

1

2345

6

123456

1

12345

1234

123456789

1

2345678

9

1

2345678

9

1

2345678

9

1

2345678

9

1

2345678

9

123456789

12345

1234

12345

123456789

1

2345678

9

1

2345678

9

1

2345678

9

1

2345678

9

1

2345678

9

123456789

12345

1234

1234567890

1

23456789

0

1

23456789

0

1

23456789

0

1

23456789

0

1234567890

12345

1234

12345

123456789

1

2345678

9

1

2345678

9

1

2345678

9

1

2345678

9

123456789

12345

123456789

1

2345678

9

1

2345678

9

1

2345678

9

1

2345678

9

123456789

12345

1234

123456789

1

2345678

9

1

2345678

9

1

2345678

9

1

2345678

9

123456789

12345

1234

CLK

ADSP\

S

ADSC\

○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○

ADDRESS A2

WEH\, WEL\,

BWE\

○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○

CE\

(See Note)

ADV\

OE\

tH

tS

tH

tKQX

tOEHZ

SINGLE WRITE BURST WRITE

GW\

○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○

DQ

BURST WRITE

t

1234

A1

12345678

123

1

2

3

1

2

3

1

2

3

1

2

3

123

1234567

12345678

1234567890123456789012345678901212345678901234

1

23456789012345678901234567890121234567890123

4

1

23456789012345678901234567890121234567890123

4

1

23456789012345678901234567890121234567890123

4

1

23456789012345678901234567890121234567890123

4

1234567890123456789012345678901212345678901234

1

12

A3

12345678

123456789012345678

1

2345678901234567

8

1

2345678901234567

8

1

2345678901234567

8

1

2345678901234567

8

123456789012345678

12

123456789012345678

S

tH

t

123456789012

123456789012345678901234567890121234567890123456789012345678901212345678901234567

1

2345678901234567890123456789012123456789012345678901234567890121234567890123456

7

1

2345678901234567890123456789012123456789012345678901234567890121234567890123456

7

1

2345678901234567890123456789012123456789012345678901234567890121234567890123456

7

1

2345678901234567890123456789012123456789012345678901234567890121234567890123456

7

123456789012345678901234567890121234567890123456789012345678901212345678901234567

1

12345

12

Q

1234

12345

1

234

5

1

234

5

12345

12

D(A2) D(A2+2) D(A2+2)

12

D(A2+3)

123

D(A3)

12

D(A3+1)

12

D(A3+2)

123456

12345

123456

12345

123456

1234

123456

1234567

123456

1234567

1

23456

7

1

23456

7

1

23456

7

1

23456

7

1234567

12

1234

12345678901234567

123456

1234

12345678901234567890123456789012123456789012345678901

1

234567890123456789012345678901212345678901234567890

1

234567890123456789012345678901212345678901234567890

1

234567890123456789012345678901212345678901234567890

1

234567890123456789012345678901212345678901234567890

1

12345678901234567890123456789012123456789012345678901

1234

12345

123456

1234567890123456789012

1

23456789012345678901

2

1

23456789012345678901

2

1

23456789012345678901

2

1

23456789012345678901

2

1234567890123456789012

1

1234

123456

D(A1) D(A2+2)

AS5SS256K18

Rev. 2.0 7/99

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

10

SSRAM

AS5SS256K18

Austin Semiconductor, Inc.

NOTE: CE\ active in this timing diagram means that all chip enables CE\, CE2, and CE2\ are active.

READ/WRITE TIMING

1234

123456789012345678901

1

2345678901234567890

1

2345678901234567890

1

2345678901234567890

1

2345678901234567890

1

123456789012345678901

12345

1234

123456789012345678

1234

1234567890

1

23456789

0

1

23456789

0

1

23456789

0

1

23456789

0

1

23456789

0

1234567890

1234

12345

123456789012

123456

1

2345

6

1

2345

6

1

2345

6

1

2345

6

1

2345

6

123456

12

CLK

ADSP\

S

ADSC\

○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○

ADDRESS A2

WEH\, WEL\,

BWE\, GW\

○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○

CE\

(See Note)

ADV\

OE\

tH

tS

tH

SINGLE READS BURST READ

○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○

DQ

BURST WRITE

t

1234

12345678

123

1

2

3

1

2

3

1

2

3

1

2

3

123

12345678

12345678901234567890123456789012123

1

234567890123456789012345678901212

3

1

234567890123456789012345678901212

3

1

234567890123456789012345678901212

3

1

234567890123456789012345678901212

3

12345678901234567890123456789012123

1

A5

12345678

1

234567

8

1

234567

8

1

234567

8

1

234567

8

12345678

12

Q(A4) Q(A4+1)

12

Q(A4+2)

123

1

Q(A4+3) D(A5) D(A5+1)

123456

1234567890123456

123456

123456789012345678901234567890121234567890123456789012345678901

1

2345678901234567890123456789012123456789012345678901234567890

1

2345678901234567890123456789012123456789012345678901234567890

1

2345678901234567890123456789012123456789012345678901234567890

1

2345678901234567890123456789012123456789012345678901234567890

1

2345678901234567890123456789012123456789012345678901234567890

1

123456789012345678901234567890121234567890123456789012345678901

1234

12345

1234567

123456789012

1

2345678901

2

1

2345678901

2

1

2345678901

2

1

2345678901

2

1

2345678901

2

123456789012

12

123456

Q(A1) D(A3)

12345

A1 A3

12345678

1234567

123

1

2

3

1

2

3

1

2

3

1

2

3

123

A4

123456

1234567890123456789012

1

123456789012345

123456

12345678901234567890123456789012123456789012

1

234567890123456789012345678901212345678901

2

1

234567890123456789012345678901212345678901

2

1

234567890123456789012345678901212345678901

2

1

234567890123456789012345678901212345678901

2

12345678901234567890123456789012123456789012

1

1234

Q(A2)

12

123

SINGLE WRITE

AS5SS256K18

Rev. 2.0 7/99

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

11

SSRAM

AS5SS256K18

Austin Semiconductor, Inc.

MECHANICAL DEFINITIONS

ASI Case #1001 (Packag e Designator DQ)

NOTE: All dimensions in Millimeters. 0.60 + 0.150.30 + 0.080.65 Basic

1.60 Max

1.40 + 0.05

16.00 + 0.10

14.00 + 0.10

22.00 + 0.10

20.00 + 0.10

AS5SS256K18

Rev. 2.0 7/99

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

12

SSRAM

AS5SS256K18

Austin Semiconductor, Inc.

EXAMPLE: AS5SS256K18DQ-8/IT

Device Number Package

Type Speed ns Process

AS5SS256K18 DQ -8 /*

AS5SS256K18 DQ -9 /*

AS5SS256K18 DQ -10 /*

ORDERING INFORMA TION

*AVAILABLE PROCESSES

IT = Industrial Temperature Range -40oC to +85oC

XT = Extended T emperature Range -55oC to +125oC