P-Channel JFET Switch calogic CORPORATION J174 - 3177 /SS1174 - SST177 FEATURES e Low Insertion Loss No Offset or Error Generated By Closed Switch = Purely Resistive = High Isolation Resistance From Driver e Short Sample and Hold Aperture Time e Fast Switching APPLICATIONS e Analog Switches Choppers e Commutators PIN CONFIGURATION TO-92 PRODUCT MARKING (SOT-23) SST174 Pod 5508 SST175 POS SST176 PO6 SST177 PO7 8-42 ABSOLUTE MAXIMUM RATINGS (Ta = 25C unless otherwise specified) Gate-Drain or Gate-Source Voliage ..........-....0. 30V Gate Current 2.0... eee ene 50mA Storage Temperature Range ............. -55C to +150C Operating Temperature Range ........... -55C to +135C Lead Temperature (Soldering, 10sec) .............. 300C Power Dissipation ........ 0.00. e eee eee eee eee 350mW Derate above 25C ......... 2. eee 3.3mW/C NOTE: Stresses above those listed under "Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ORDERING INFORMATION Part Package Temperature Range J174-J177 Plastic TO-92 -55C to +135C SST174-SST177 Plastic SOT-23 ~55C to +135C For Sorted Chips in Carriers see 2N5114 series.174 -J177 /SST174 SS1177 calogic J / ELECTRICAL CHARACTERISTICS (Ta = 25C unless otherwise specified) 174 175 we O{ aa MIN|TYP/MAX| MIN |TYP|MAX| MIN|TYP/MAX MIN |TYPIMAX SYMBOL| PARAMETER UNITS TEST CONDITIONS Gate Reverse less Current 1 1 1 1 nA |Vos = 0, Vas = 20V (Note 1} Gate Source Cutoff Voltage Vasiatt 5 10] 3 6) 1 4 [08 2.25 Vos = -15V, Ip =-10nA Gate Source BVess | Breakdown 30 30 30 30 Vos = 0, Ia = 1pA Voltage Drain Saturation Current (Note 2) Drain Cutoff lo (otf Current - 1 -1 1 nA |Vps = -15V, Vas = 10V (Note 1) Drain-Source ON Resistance Drain-Gate Cdgiot) 99 JOFF 5.5 5.5 5.5 5.8 Capacitance Vos = 0, Source-Gate Vas = 10V Cegios) = [OFF 5.5 5.5 5.5 5.5 pE f = 1MHz (Note 3) Capacitance Ipss -20 135] -7 -70] -2 -35 |-1.5 -20] mA Vos = -15V, Vas = 0 TDS{(on) 85 125 250 300} 2 [Vas =0, Vos =-0.1V Drain-Gate Cagion) | Plus Source 39 + Csgion) |Gate ON Capacitance 32 32 32 Vos = Vas = 0 sali On Delay 2 5 15 20 saltching Time Test Conditions le t Rise Ti 174 175 176 177 r ise Time 5 10 20 25 ns |Voo 40V. BV -6V 6V Turn Off Delay 5 10 15 20 Vesti) 12V 8v 3V 3V Time RL 5602 12k2 5.6kQ 10k Vasion) OV OV ov ov ta(on) tdfoffy tt Fall Time 10 20 20 25 NOTES: 1. Approximately doubles for every 10C increase in Ta. 2. Pulse test duration -300us; duty cycle <3%, 3. For design reference only, not 100% tested. 8-43