BSS63LT1 - ON Semiconductor - Datasheet.Online

High Voltage Transistor

PNP Silicon

MAXIMUM RATINGS

Rating Symbol Value Unit

Collector–Emitter Voltage VCEO –100 Vdc

Collector–Emitter Voltage

RBE = 10 kΩVCER –110 Vdc

Collector Current — Continuous IC–100 mAdc

THERMAL CHARACTERISTICS

Characteristic Symbol Max Unit

Total Device Dissipation FR–5 Board(1)

TA = 25°C

Derate above 25°C

PD225

1.8

mW/°C

Thermal Resistance Junction to Ambient RJA 556 °C/W

Total Device Dissipation

Alumina Substrate,(2) TA = 25°C

Derate above 25°C

PD300

2.4

mW/°C

Thermal Resistance, Junction to Ambient RJA 417 °C/W

Junction and Storage Temperature TJ, Tstg –55 to +150 °C

DEVICE MARKING

BSS63LT1 = T1

ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)

Characteristic Symbol Min Typ Max Unit

OFF CHARACTERISTICS

Collector–Emitter Breakdown Voltage

(IC = –100 µAdc) V(BR)CEO –100 — — Vdc

Collector–Emitter Breakdown Voltage

(IC = –10 µAdc, IE = 0, RBE = 10 kΩ)V(BR)CER –110 — — Vdc

Collector–Base Breakdown Voltage

(IE = –10 Adc, IE = 0) V(BR)CBO –110 — — Vdc

Emitter–Base Breakdown Voltage

(IE = –10 Adc) V(BR)EBO –6.0 — — Vdc

Collector Cutoff Current

(VCB = –90 Vdc, IE = 0) ICBO — — –100 nAdc

Collector Cutoff Current

(VCE = –110 Vdc, RBE = 10 kΩ)ICER — — –10 µAdc

Emitter Cutoff Current

(VEB = –6.0 Vdc, IC = 0) IEBO — — –200 nAdc

1. FR–5 = 1.0  0.75  0.062 in.

2. Alumina = 0.4  0.3  0.024 in. 99.5% alumina.

ON Semiconductor

 Semiconductor Components Industries, LLC, 2001

November, 2001 – Rev. 3 1Publication Order Number:

BSS63LT1/D

BSS63LT1

CASE 318–08, STYLE 6

SOT–23 (TO–236AB)

COLLECTOR

BASE

EMITTER

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ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) (Continued)

Characteristic Symbol Min Typ Max Unit

ON CHARACTERISTICS

DC Current Gain

(IC = –10 mAdc, VCE = –1.0 Vdc)

(IC = –25 mAdc, VCE = –1.0 Vdc)

hFE 30

30 —

——

—

Collector–Emitter Saturation Voltage

(IC = –25 mAdc, IB = –2.5 mAdc) VCE(sat) — — –250 mVdc

Base–Emitter Saturation Voltage

(IC = –25 mAdc, IB = –2.5 mAdc) VBE(sat) — — –900 mVdc

SMALL–SIGNAL CHARACTERISTICS

Current–Gain — Bandwidth Product

(IC = –25 mAdc, VCE = –5.0 Vdc, f = 20 MHz) fT50 95 — MHz

Case Capacitance

(IE = IC = 0, VCB = –10 Vdc, f = 1.0 MHz) CC— — 20 pF

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The values for the equation are found in the maximum

ratings table on the data sheet. Substituting these values

into the equation for an ambient temperature TA of 25°C,

one can calculate the power dissipation of the device which

in this case is 225 milliwatts.

INFORMATION FOR USING THE SOT–23 SURFACE MOUNT PACKAGE

MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS

Surface mount board layout is a critical portion of the

total design. The footprint for the semiconductor packages

must be the correct size to insure proper solder connection

interface between the board and the package. With the

correct pad geometry, the packages will self align when

subjected to a solder reflow process.

SOT–23

inches

0.037

0.95

0.037

0.95

0.079

2.0

0.035

0.9

0.031

0.8

SOT–23 POWER DISSIPATION

PD = TJ(max) – TA

RθJA

PD = 150°C – 25°C

556°C/W = 225 milliwatts

The power dissipation of the SOT–23 is a function of the

pad size. This can vary from the minimum pad size for

soldering to a pad size given for maximum power dissipa-

tion. Power dissipation for a surface mount device is deter-

mined b y T J(max), the maximum rated junction temperature

of the die, RθJA, the thermal resistance from the device

junction to ambient, and the operating temperature, TA.

Using the values provided on the data sheet for the SOT–23

package, PD can be calculated as follows:

The 556°C/W for the SOT–23 package assumes the use

of the recommended footprint on a glass epoxy printed

circuit board to achieve a power dissipation of 225 milli-

watts. There are other alternatives to achieving higher

power dissipation from the SOT–23 package. Another

alternative would be to use a ceramic substrate or an

aluminum core board such as Thermal Clad. Using a

board material such as Thermal Clad, an aluminum core

board, the power dissipation can be doubled using the same

footprint.

SOLDERING PRECAUTIONS

The melting temperature of solder is higher than the

rated temperature of the device. When the entire device is

heated to a high temperature, failure to complete soldering

within a short time could result in device failure. There-

fore, the following items should always be observed in

order to minimize the thermal stress to which the devices

are subjected.

•Always preheat the device.

•The delta temperature between the preheat and

soldering should be 100°C or less.*

•When preheating and soldering, the temperature of the

leads and the case must not exceed the maximum

temperature ratings as shown on the data sheet. When

using infrared heating with the reflow soldering

method, the difference shall be a maximum of 10°C.

•The soldering temperature and time shall not exceed

260°C for more than 10 seconds.

•When shifting from preheating to soldering, the

maximum temperature gradient shall be 5°C or less.

•After soldering has been completed, the device should

be allowed to cool naturally for at least three minutes.

Gradual cooling should be used as the use of forced

cooling will increase the temperature gradient and

result in latent failure due to mechanical stress.

•Mechanical stress or shock should not be applied

during cooling.

* Soldering a device without preheating can cause exces-

sive thermal shock and stress which can result in damage

to the device.

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PACKAGE DIMENSIONS

CASE 318–08

ISSUE AE

SOT–23 (TO–236AB)

DIM

MIN MAX MIN MAX

MILLIMETERS

0.1102 0.1197 2.80 3.04

INCHES

B0.0472 0.0551 1.20 1.40

C0.0350 0.0440 0.89 1.11

D0.0150 0.0200 0.37 0.50

G0.0701 0.0807 1.78 2.04

H0.0005 0.0040 0.013 0.100

J0.0034 0.0070 0.085 0.177

K0.0140 0.0285 0.35 0.69

L0.0350 0.0401 0.89 1.02

S0.0830 0.1039 2.10 2.64

V0.0177 0.0236 0.45 0.60

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. MAXIMUM LEAD THICKNESS INCLUDES LEAD

FINISH THICKNESS. MINIMUM LEAD THICKNESS

IS THE MINIMUM THICKNESS OF BASE

MATERIAL.

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PUBLICATION ORDERING INFORMATION

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4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–0031

Phone: 81–3–5740–2700

Email: r14525@onsemi.com

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Sales Representative.

BSS63LT1/D

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