LT4430
1
4430fd
For more information www.linear.com/LT4430
Typical applicaTion
FeaTures DescripTion
Secondary-Side
Opto-Coupler Driver
The LT
®
4430 drives the opto-coupler that crosses the gal-
vanic barrier in an isolated power supply. The IC contains
a precision-trimmed reference, a high bandwidth error
amplifier, an inverting gain of 6 stage to drive the opto-
coupler and unique overshoot control circuitry.
The LT4430’s 600mV reference provides ±0.75% initial
accuracy and ±1.25% tolerance over temperature. A high
bandwidth 9MHz error amplifier permits simple frequency
compensation and negligible phase shift at typical loop
crossover frequencies. The opto-coupler driver provides
10mA of output current and is short-circuit protected.
A unique overshoot control function prevents output
overshoot on start-up and short-circuit recovery with a
single capacitor.
The LT4430 is available in the low profile 6-lead TSOT-23
package.
applicaTions
n 600mV Reference (1.25% Over Temperature)
n Wide Input Supply Range: 3V to 20V
n Overshoot Control Function Prevents Output
Overshoot on Start-Up and Short-Circuit Recovery
n High Bandwidth Error Amplifier Permits Simple Loop
Frequency Compensation
n Ground-Referenced Opto-Coupler Drive
n 10mA Opto-Coupler Drive with Current Limiting
n Low Profile (1mm) ThinSOT
TM
Package
n 48V Input Isolated DC/DC Converters
n Isolated Telecommunication Power Systems
n Distributed Power Step-Down Converters
n Offline Isolated Power Supplies
n Industrial Control Systems
n Automotive and Heavy Equipment L, LT , LT C , LT M , Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. ThinSOT is a trademark of Linear Technology Corporation. All other
trademarks are the property of their respective owners.
Simplified Isolated Synchronous Forward Converter
Isolated Flyback Telecom Converter
Start-Up with Overshoot Control
(See Schematic on Back Page)
•
•
+
••
VIN
4430 TA01
+
VOUT
VCC
VCC VIN OPTO
GND COMP
OC FB
LTC3900
SYNC
CGFG
LT4430
ISOLATION
BARRIER
LT1952
VIN
50V/DIV
VOUT
5V/DIV
OVERSHOOT CONTROL
IMPLEMENTED
t = 5ms/DIV 4430 TA01b
LT4430
2
4430fd
For more information www.linear.com/LT4430
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LT4430ES6#PBF LT4430ES6#TRPBF LTBFY 6-Lead Plastic TSOT-23 –40°C to 125°C
LT4430IS6#PBF LT4430IS6#TRPBF LTBFY 6-Lead Plastic TSOT-23 –40°C to 125°C
LT4430HS6#PBF LT4430HS6#TRPBF LTBFY 6-Lead Plastic TSOT-23 –40°C to 150°C
LT4430MPS6#PBF LT4430MPS6#TRPBF LTBFY 6-Lead Plastic TSOT-23 –55°C to 150°C
LEAD BASED FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LT4430ES6 LT4430ES6#TR LTBFY 6-Lead Plastic TSOT-23 –40°C to 125°C
LT4430IS6 LT4430IS6#TR LTBFY 6-Lead Plastic TSOT-23 –40°C to 125°C
LT4430HS6 LT4430HS6#TR LTBFY 6-Lead Plastic TSOT-23 –40°C to 150°C
LT4430MPS6 LT4430MPS6#TR LTBFY 6-Lead Plastic TSOT-23 –55°C to 150°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
absoluTe MaxiMuM raTings
orDer inForMaTion
Supply Voltage
VIN ........................................................................20V
FB Voltage .................................................... –0.3V to 6V
OPTO Short-Circuit Duration ............................ Indefinite
Operating Junction Temperature Range (Note 2)
E-, I-Grades ....................................... –40°C to 125°C
H-Grade ............................................. –40°C to 150°C
MP-Grade .......................................... –55°C to 150°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec) ...................300°C
(Note 1)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN Input Voltage Range ●3 20 V
IIN Supply Current 3V ≤ VIN ≤ 20V (E-, I-Grades)
3V ≤ VIN ≤ 20V (H-, MP-Grades)
●1.9
1.9
3.9
4.3
mA
mA
VUVLO Undervoltage Lockout Threshold OC Held Low for VIN < VUVLO (E-, I-Grades)
OC Held Low for VIN < VUVLO (H-Grade)
OC Held Low for VIN < VUVLO (MP-Grade)
●
●
●
1.95
1.9
1.9
2.2
2.2
2.2
2.5
2.5
2.55
V
V
V
VFB Feedback Reference Voltage
3V ≤ VIN ≤ 20V
●
0.5955
0.5925
0.6
0.6
0.6045
0.6075
V
V
VFB Line Regulation 3V ≤ VIN ≤ 20V 0.02 0.1 %
IFB FB Input Bias Current FB = VFB –150 –75 nA
pin conFiguraTion
1
2
3
6
5
4
TOP VIEW
S6 PACKAGE
6-LEAD PLASTIC TSOT-23
OPTO
COMP
FB
VIN
GND
OC
TJMAX = 125°C, θJA = 250°C/W
The ● denotes the specifications which apply over the full operating junction
temperature range, otherwise specifications are at TA = 25°C. VIN = 5V, FB = VFB, COMP = 1V, unless otherwise noted (Note 3).
elecTrical characTerisTics
LT4430
3
4430fd
For more information www.linear.com/LT4430
The ● denotes the specifications which apply over the full operating junction
temperature range, otherwise specifications are at TA = 25°C. VIN = 5V, FB = VFB, COMP = 1V, unless otherwise noted (Note 3).
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT4430 is tested under pulsed load conditions such that TJ ≈ TA.
The LT4430E is guaranteed to meet specifications from 0°C to 125°C
junction temperature. Specifications over the –40°C to 125°C operating
junction temperature range are assured by design, characterization and
correlation with statistical process controls. The LT4430I is guaranteed
over the –40°C to 125°C operating junction temperature range, the
LT4430H is guaranteed over the –40°C to 150°C operating junction
temperature range and the LT4430MP is tested and guaranteed over
the –55°C to 150°C operating junction temperature range. High junction
temperatures degrade operating lifetimes; operating lifetime is derated
for junction temperatures greater than 125°C. Note that the maximum
ambient temperature consistent with these specifications is determined by
specific operating conditions in conjunction with board layout, the rated
package thermal impedance and other environmental factors.
Note 3: All currents into device pins are positive. All currents out of device
pins are negative. All voltages are referenced to GND unless otherwise
specified.
Note 4: This parameter is guaranteed by correlation and is not tested.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
IOC Overshoot Control Charging Current VOC = 0V (E-, I-Grades)
VOC = 0V (H-Grade)
VOC = 0V (MP-Grade)
●
●
●
–15
–17
–17
–8.5
–8.5
–8.5
–5
–5
–4
µA
µA
µA
OC Clamp Voltage 0.93 V
OC Amplifier Offset Voltage FB = 0.3V 48 mV
AVOL Error Amplifier Open-Loop DC Gain VCOMP = 0.8V to 1V (E-, I-Grades)
VCOMP = 0.8V to 1V (H-, MP-Grades)
●
●
60
55
80
80
dB
dB
Error Amplifier Unity-Gain Bandwidth No Load (Note 4) 9 MHz
Error Amplifier Output Swing Low FB = 1V ●0.1 0.35 0.55 V
Error Amplifier Output Swing High FB = 0V (E-, I-Grades)
FB = 0V (H-Grade)
FB = 0V (MP-Grade)
●
●
●
1.2
1.2
1.15
1.33
1.33
1.33
1.5
1.55
1.55
V
V
V
Error Amplifier Output Source Current FB = 0V, COMP = 1V (E-, I-Grades)
FB = 0V, COMP = 1V (H-Grade)
FB = 0V, COMP = 1V (MP-Grade)
●
●
●
–800
–825
–825
–450
–450
–450
–225
–225
–200
µA
µA
µA
Error Amplifier Output Sink Current FB = 1V, COMP = 1V 25 mA
Opto Driver Inverting DC Gain –6.4 –6 –5.6 V/V
Opto Driver –3dB Bandwidth No Load (Note 4) 600 kHz
Opto Driver Output Swing Low FB = 0V, COMP = Open (E-, I-Grades)
FB = 0V, COMP = Open (H-, MP-Grades)
●
●
0.5
0.5
0.85
0.9
V
V
Opto Driver Output Swing High VIN = 3V, FB = 1V, COMP = Open,
IOPTO = 10mA (E-, I-, H-Grades)
VIN = 3V, FB = 1V, COMP = Open,
IOPTO = 10mA (MP-Grade)
●
●
VIN – 1.25
VIN – 1.3
VIN – 1.05
VIN – 1.05
V
V
Opto Driver Output Swing High VIN = 20V, FB = 1V, COMP = Open,
IOPTO = 10mA
●4.2 5.6 7.5 V
ISC Opto Driver Output
Short-Circuit Current (Sourcing)
FB = 1V, COMP = Open, OPTO = 0V
(E-, I-, H-Grades)
FB = 1V, COMP = Open, OPTO = 0V
(MP-Grade)
●
●
10.5
9.5
22
22
45
45
mA
mA
Opto Driver Output Sink Current FB = 0V, OPTO = 1.5V (E-, I-, H-Grades)
FB = 0V, OPTO = 1.5V (MP-Grade)
●
●
150
135
350
350
650
650
µA
µA
elecTrical characTerisTics
LT4430
4
4430fd
For more information www.linear.com/LT4430
Typical perForMance characTerisTics
Feedback Reference Voltage
vs Temperature
FB Voltage Line Regulation
FB Input Bias Current
vs Temperature
TEMPERATURE (°C)
–75 –50
0.594
0.595
VFB (V)
0.596
0.598
0.600
0.602
0 50 100 150
4430 G03
0.604
0.597
0.599
0.601
0.603
0.605
0.606
–25 25 75 125
VIN (V)
0
0.5990
VFB (V)
0.5995
0.6000
0.6005
4 8 12 20
4430 G04
0.6010
2 6 10 14 16 18
TA = 25°C
TEMPERATURE (°C)
–75 –50
–200
–175
FB INPUT BIAS CURRENT (nA)
–150
–100
–50
0
0 50 100 150
4430 G05
–125
–75
–25
25
50
–25 25 75 125
OC Charging Current
vs Input Voltage
OC Charging Current
vs Temperature
OC Clamp Voltage
vs Temperature
OC Amplifier Offset Voltage
vs Temperature
VIN (V)
0
OC CHARGING CURRENT (µA)
5 10 15
4430 G06
20
15
13
11
9
7
5
TEMPERATURE (°C)
–75 –50
5
OC CHARGING CURRENT (µA)
7
9
11
13
0 50 100 150
4430 G07
15
–25 25 75 125
VIN = 5V
TEMPERATURE (°C)
–75 –50
0.5
OC CLAMP VOLTAGE (V)
0.7
0.9
1.1
1.3
0 50 100 150
4430 G08
1.5
–25 25 75 125
TEMPERATURE (°C)
–75 –50
0
10
VOC – VFB (mV)
20
40
60
80
0 50 100 150
4430 G09
30
50
70
90
100
–25 25 75 125
Quiescent Current vs Temperature
Undervoltage Lockout Threshold
vs Temperature
TEMPERATURE (°C)
–50–75
1.0
QUIESCENT CURRENT (mA)
1.5
2.0
2.5
3.0
0 50 100 150
4430 G01
3.5
4.0
–25 25 75 125
VIN = 3V
VIN = 20V
TEMPERATURE (°C)
–75 –50
1.0
VUVLO (V)
1.5
2.0
2.5
0 50 100 150
4430 G02
3.0
–25 25 75 125
LT4430
5
4430fd
For more information www.linear.com/LT4430
Typical perForMance characTerisTics
Error Amplifier Output Swing Low
vs Temperature
Error Amplifier Output Swing High
vs Temperature
Error Amplifier Open Loop Gain
and Phase vs Frequency
TEMPERATURE (°C)
–75 –50
0
ERROR AMPLIFIER OUTPUT SWING LOW (V)
0.1
0.2
0.3
0.4
0 50 100 150
4430 G11
0.5
–25 25 75 125
Error Amplifier Output Source
Current vs Temperature
TEMPERATURE (°C)
–75 –50
0
100
ERROR AMPLIFIER OUTPUT SOURCE CURRENT (µA)
200
400
600
800
0 50 100 150
4430 G13
300
500
700
900
1000
–25 25 75 125
FREQUENCY (Hz)
1k
–20
GAIN (dB)
0
20
40
60
–10
10
30
50
50M10M
4430 G10
80
70
–45
PHASE (°)
0
45
90
135
180
10k 100k 1M
PHASE
GAIN
TEMPERATURE (°C)
–75 –50
1.0
ERROR AMPLIFIER OUTPUT SWING HIGH (V)
1.1
1.2
1.3
1.4
0 50 100 150
4430 G12
1.5
–25 25 75 125
Opto Driver Inverting DC Gain
vs Temperature
Opto Driver Inverting Closed Loop
Gain and Phase vs Frequency
Error Amplifier Output Sink
Current vs Temperature
TEMPERATURE (°C)
–75 –50
0
ERROR AMPLIFIER OUTPUT SINK CURRENT (mA)
10
20
30
40
0 50 100 150
4430 G14
50
–25 25 75 125
TEMPERATURE (°C)
–75 –50
5.6
OPTO DRIVER INVERTING DC GAIN (V/V)
5.7
5.8
6.0
6.2
0 50 100 150
4430 G15
6.4
5.9
6.1
6.3
–25 25 75 125
FREQUENCY (Hz)
1k
–10
GAIN (dB)
0
10
20
30
–5
5
15
25
10M
4430 G16
40
35
–45
PHASE (°)
0
45
90
135
180
10k 100k 1M
PHASE
GAIN
LT4430
6
4430fd
For more information www.linear.com/LT4430
Typical perForMance characTerisTics
Opto Driver Output Swing Low
vs Temperature
Opto Driver Output Swing High
vs Temperature
Opto Driver Output Swing High
vs Temperature
Opto Driver Output Sink Current
vs Temperature
Opto Driver Output Short-Circuit
Current (Sourcing) vs Temperature
TEMPERATURE (°C)
–75 –50
0
100
OPTO DRIVER OUTPUT SINK CURRENT (µA)
200
400
600
800
0 50 100 150
4430 G20
300
500
700
900
1000
–25 25 75 125
TEMPERATURE (°C)
–75 –50
0
0.1
OPTO DRIVER OUTPUT SWING LOW (V)
0.2
0.4
0.6
0.8
0 50 100 150
4430 G17
0.3
0.5
0.7
0.9
1.0
–25 25 75 125
TEMPERATURE (°C)
–75 –50
0.5
0.6
VIN – VOPTO (V)
0.7
0.9
1.1
1.3
0 50 100 150
4430 G18
0.8
1.0
1.2
1.4
1.5
–25 25 75 125
VIN = 3V
IOPTO = 10mA
TEMPERATURE (°C)
–75 –50
4.0
OPTO DRIVER OUTPUT SWING HIGH (V)
5.0
6.0
7.0
0 50 100 150
4430 G19
4.5
5.5
6.5
7.5
8.0
–25 25 75 125
VIN = 20V
IOPTO = 10mA
TEMPERATURE (°C)
–75 –50
0
OPTO DRIVER SHORT-CIRCUIT CURRENT (mA)
10
20
30
0 50 100 150
4430 G21
40
–25 25 75 125
LT4430
7
4430fd
For more information www.linear.com/LT4430
pin FuncTions
VIN (Pin 1): This is the input supply that powers all internal
circuitry. The input supply range is 3V minimum to 20V
maximum and the typical input quiescent current is 1.9mA.
Connect a 1µF bypass capacitor directly from VIN to GND.
GND (Pin 2): Analog Ground Pin. It is also the negative
sense terminal for the internal 0.6V reference. Connect the
external feedback divider network that terminates to ground
directly to this pin for best regulation and performance.
OC (Pin 3): Overshoot Control Pin. A typical 8.5µA current
source and a capacitor placed from this pin to GND controls
output voltage overshoot on start-up and recovery from
short-circuit. The typical ramp time is (COC • 0.6V)/8.5µA.
If VIN is below VUVLO (its undervoltage lockout threshold),
the OC pin is actively held low. The OC pin also ties to the
overshoot control amplifier output. This amplifier monitors
the FB pin voltage and the error amplifier output. If FB is
low due to a short-circuit fault condition, the COMP pin
goes high. Logic detects the error amplifier COMP pin high
state and activates the overshoot control amplifier. The
amplifier responds by discharging the OC capacitor down
to the FB voltage plus a built-in offset voltage of 48mV. If
the short-circuit condition persists, the amplifier maintains
the voltage on OC. If the short-circuit condition goes away,
the FB pin recovers under the control of the OC pin.
FB (Pin 4): This is the inverting input of the error ampli-
fier. The noninverting input is tied to the internal 0.6V
reference. Input bias current for this pin is typically 75nA
flowing out of the pin. This pin normally ties to a resistor
divider network to set output voltage. Tie the top of the
external resistor divider directly to the output voltage for
best regulation performance.
COMP (Pin 5): This is the output of the error amplifier. The
error amplifier is a true voltage-mode error amplifier and
frequency compensation is performed around the amplifier.
Typical LT4430 compensation schemes use series R-C in
parallel with C networks from the COMP pin to the FB pin.
COMP also ties to the overshoot control amplifier logic
that detects if the COMP pin is at its high clamp level. The
logic activates the overshoot control amplifier if COMP is
at its clamp level for longer than 1µs.
OPTO (Pin 6): This is the output of the amplifier that
drives the opto-coupler. The opto driver amplifier uses an
inverting gain of six configuration to drive the opto-coupler
referenced to ground. Driving the opto-coupler referenced
to GND accommodates low output voltages and eases
loop frequency compensation as the secondary feedback
path with a traditional “431” topology is eliminated. The
opto driver amplifier sources a maximum of 10mA, sinks
350µA typically and is short-circuit protected.
LT4430
9
4430fd
For more information www.linear.com/LT4430
applicaTions inForMaTion
Block Diagram Operation
A precision voltage reference, a high-bandwidth error am-
plifier, an inverting opto-coupler driver and an overshoot
control amplifier comprise the LT4430. Referring to the
block diagram, a start-up circuit establishes all internal
current and voltage biasing for the IC. A precision-trimmed
bandgap generates the 600mV reference voltage and a
1.1V bias voltage for the opto-coupler driver. Room tem-
perature reference voltage accuracy is specified at ±0.75%
and operating temperature range tolerance is specified at
±1.25%. The 600mV reference ties to the noninverting
input of the error amplifier.
The LT4430 error amplifier senses the output voltage
through an external resistor divider and regulates the FB
pin to 600mV. The FB pin ties to the inverting input of
the error amplifier. The error amplifier’s open loop DC
gain is 80dB and its unity-gain crossover frequency of
9MHz provides negligible phase shift at typical feedback
loop crossover frequencies. The error amplifier is a true
voltage-mode amplifier and frequency compensation con-
nects around the amplifier. Typical LT4430 compensation
schemes use series R-C in parallel with C networks from
the COMP pin to the FB pin.
The opto-coupler driver amplifies the voltage difference
between the COMP pin and the 1.1V bias potential applied
to its noninverting terminal with an inverting gain of 6. This
signal drives the opto-coupler referenced to GND. Driving
the opto-coupler referenced to GND accommodates low
output voltages and simplifies loop frequency compen-
sation as the secondary feedback path with a traditional
“431” topology is eliminated. A resistor in series with the
opto-coupler sets the opto-coupler’s DC bias current. The
opto driver amplifier sources a guaranteed maximum of
10mA, sinks 350µA typically and is short-circuit protected.
The opto-coupler driver amplifier’s typical –3dB band-
width is 600kHz. The opto-coupler’s output crosses the
galvanic isolation barrier and closes the feedback loop to
the primary-side controller.
The LT4430 incorporates a unique overshoot control
function that allows the user to ramp the output voltage
on start-up and recovery from short-circuit conditions,
preventing overshoot. A capacitor, connected from the OC
pin to GND and charged by internal 8.5µA current source
IOC, sets the ramp rate. On start-up, Q1 actively holds
the OC capacitor low until VIN of the LT4430 reaches its
typical undervoltage lockout threshold of 2.2V. Q1 then
turns off and the OC capacitor charges linearly. Q2 and Q3
OR the OC pin voltage and the 600mV reference voltage
at the noninverting terminal of the error amplifier. The OC
pin voltage is the reference voltage for the error amplifier
until it increases above 600mV. If the feedback loop is in
control, the FB pin voltage follows and regulates to the OC
pin voltage. As the OC pin voltage increases past 600mV,
the reference voltage takes control of the error amplifier
and the FB pin regulates to 600mV. The OC pin voltage
increases until it is internally clamped by R2, Q6 and V1.
The OC pin’s typical clamp voltage of 0.93V ensures that
Q3 turns off. All of I1’s current flows in Q2, matching I2’s
current in Q4.
In a short-circuit condition, the output voltage decreases
to something well below the regulated level. The error am-
plifier reacts by increasing the COMP pin voltage, thereby
decreasing the drive to the opto-coupler. The decreased
opto-coupler bias signals the primary-side controller to
increase the amount of power it delivers in an attempt to
raise the output voltage back to its regulated value. As
long as the fault persists, the output voltage remains low.
The error amplifier’s COMP pin voltage increases until it
reaches a clamp level set by Q7 and V2. Q7’s resultant
collector current drives internal logic that closes normally
open switch S1. This action activates the overshoot control
amplifier which employs a unity-gain follower configura-
tion. The overshoot control amplifier monitors the FB pin
voltage and, on S1’s closing, pulls the OC pin voltage
down to the FB pin voltage plus a built-in offset voltage
of typically 48mV. The built-in offset voltage serves two
purposes. First, the offset voltage prevents the overshoot
control amplifier from interfering with normal transient
operating conditions. Second, the offset voltage biases
the feedback loop so that if the short-circuit condition
ends, the feedback loop immediately starts to increase
the output voltage to its regulated value.
LT4430
10
4430fd
For more information www.linear.com/LT4430
applicaTions inForMaTion
If the fault condition ceases, the output voltage increases.
In response, the error amplifier COMP pin’s voltage
decreases. This action opens switch S1, deactivates the
overshoot control amplifier and allows the OC pin capacitor
to charge. The FB pin voltage increases quickly until the
FB pin voltage exceeds the OC pin voltage. The feedback
loop increases the drive to the opto-coupler until the FB
pin follows and regulates to the OC pin voltage. Again, as
the OC pin voltage increases past 600mV, the reference
voltage takes control of the error amplifier and the FB pin
regulates to 600mV.
Generating a VIN Bias Supply
Biasing an LT4430 is crucial to proper operation. If the
overshoot control (OC) function is not being used and the
output voltage is greater than 3.3V, the IC may be biased
from VOUT. In these cases, it is the user’s responsibility
to verify large-signal start-up and fault recovery behavior.
If the overshoot control function is being used or the
output voltage is below the LT4430’s minimum operat-
ing voltage of 3V, employing an alternate bias method is
necessary. The LT4430’s undervoltage lockout (UVLO)
circuitry, controlled by VIN, resets and holds the OC pin
capacitor low for VIN less than 2.2V. When VIN increases
above 2.2V, the circuit releases the OC pin capacitor. The
LT4430’s supply voltage must come up faster than the
output voltage to assert loop control and limit output volt-
age overshoot. In most cases, a few simple components
accomplish this task. Adding a few biasing components
to control overshoot is advantageous. Let’s examine bias
circuits for different topologies.
Figures 1a to 1e illustrate bias supply circuits for the
flyback converter. Figure 1a shows the typical flyback
output connection. Figures 1b and 1c exhibit equivalent
circuit performance but rotate the rectifier connection to
the ground-referred side. This connection permits the user
to take advantage of the transformer secondary’s forward
behavior when the primary-side switch is on.
Figures 1d to 1e illustrate the bias generator circuit.
VIN • N volts appear across the secondary winding when
the primary-side switch is on. D2 forward biases and C1
charges. During this time, the secondary-voltage is in
series with VOUT and C1 ultimately charges to (VIN • N +
VOUT – VF). VF is the forward voltage of D2. When VOUT
is zero at start-up, VIN • N volts exists to charge C1. C1 is
generally much smaller in value than COUT and the bias
supply starts up ahead of VOUT. R1 in Figures 1d and
1e limits peak charging currents, lowering D2’s current
rating. R1 also filters C1 from peak-charging to the volt-
age spikes induced by the secondary winding’s leakage
inductance. Between 1Ω to 10Ω is generally sufficient. R1
is usually necessary if C1 is a low ESR ceramic capacitor
or if the transformer has high leakage inductance. It may
be possible to eliminate R1 if C1 is a low cost, high ESR,
surface-mount tantalum.
VIN variation changes the bias supply in Figure 1d. Depend-
ing on VOUT, the transformer turns ratio N and VIN range,
the bias supply may exceed the LT4430’s 20V VIN absolute
maximum rating. If this occurs, two solutions exist. One
is to tap the secondary-side inductor to create a lower
voltage from which to rectify as illustrated in Figure 2a.
The bias voltage decreases to (VIN • N1/N + VOUT – VF).
This solution relies on secondary-side pins being available
for the tap point.
LT4430
11
4430fd
For more information www.linear.com/LT4430
applicaTions inForMaTion
•
•
VIN
4430 F01a
T1
1:N
VOUT
COUT
D1
•
•
VIN
4430 F01b
T1
1:N
VOUT
COUT
D1
•
•
VIN
4430 F01c
Tx1
1:N
VOUT
COUT
SYNC
Q1 •
•
VIN
4430 F01d
T1
1:N
VOUT
COUT
*OPTIONAL SEE TEXT
LT4430
VBIAS
C1
R1*
D2
D1
•
•
VIN
4430 F01e
T1
1:N
VOUT
COUT
*OPTIONAL SEE TEXT
SYNC
Q1
LT4430
VBIAS
C1
R1*
D2
Figure 1a. Typical Flyback Converter Connection Figure 1b. Equivalent Flyback Converter Connection
Figure 1c. Synchronous Flyback Converter Connection Figure 1d. Flyback Converter with Bias Generator
Figure 1e. Synchronous Flyback with Bias Generator
LT4430
12
4430fd
For more information www.linear.com/LT4430
The second solution is to make a preregulator as shown
in Figure 2b. In this example, the bias supply equals (VZ1
– VBE). Select R2 to bias Zener diode Z1 and to supply
base current to QBS. Resistor R3 (on the order of a few
hundred ohms), in series with Q5’s base, suppresses
possible high frequency oscillations depending on QBS’s
selection. The preregulator circuit has additional value for
fully synchronous converters. Fully synchronous convert-
ers require gate drivers to control the secondary-side
applicaTions inForMaTion
MOSFETs turn on and turnoff. The gate driver circuitry
requires supply current in the range of 10mA to 100mA
depending on the gate driver supply voltage, MOSFET size
and switching frequency. The preregulator bias supply is
ideal for powering both the LT4430 and the gate driver
circuitry, especially since the gate drivers typically use a
supply voltage between 5V to 12V. The preregulator circuit
finds wide use in fully synchronous forward converters,
push-pull converters and full-bridge converters.
•
4430 F02a
T1
N2
N1
1:N
N = N1 + N2
VOUT
COUT
*OPTIONAL SEE TEXT
•
LT4430
VBIAS
C1
R1*
D2
D1
••
VIN
•
•
VIN
4430 F02b
T1
1:N
VOUT
LT4430
VBIAS
COUT
C1
R1*
D2
C2
*OPTIONAL SEE TEXT
D1
R3*
R2
QBS
Z1
Figure 2a. Flyback Converter with Tapped Secondary Bias
Figure 2b. Flyback Converter with Preregulator Bias
LT4430
13
4430fd
For more information www.linear.com/LT4430
applicaTions inForMaTion
•
•
VIN
4430 F03a
T1
1:N
VOUT
COUT
CG
*OPTIONAL SEE TEXT
L1
Q2
FGQ1
LT4430
VBIAS
C1
R1*
D1
4430 F03b
•
•
T1
N1
N2
1:N
N = N1 + N2
VOUT
COUT
CG
*OPTIONAL SEE TEXT
L1
Q2
LT4430
VBIAS
C1
R1*
D1
••
VIN
FGQ1
•
•
VIN
4430 F03c
T1
1:N
VOUT
LT4430
VBIAS
COUT
C1
R1*
D1
C2
CG
*OPTIONAL SEE TEXT
L1
Q2
FGQ1
R3*
R2
QBS
Z1
Figure 3a. Typical Single-Switch Synchronous Forward
Converter with Bias Generator
Figure 3b. Single-Switch Synchronous Forward Converter
with Tapped Secondary Bias Generator
Figure 3c. Single-Switch Synchronous Forward Converter
with Preregulator Bias Generator
Generate a bias supply for a forward converter using similar
techniques to that of the flyback converter. Figure 3a to 3c
detail the three common bias circuits for the synchronous
single-switch forward converter. In the flyback converter
of Figure 1d, the bias supply is proportional to VIN and
VOUT. However, in the forward converter, L1’s presence
decouples the bias supply from VOUT. In Figure 3a, the
bias supply equals (VIN • N – VF). In Figure 3b, the bias
supply equals (VIN • N1/N – VF). In Figure 3c, the bias
supply equals (VZ1 – VF).
LT4430
14
4430fd
For more information www.linear.com/LT4430
applicaTions inForMaTion
Figures 4a to 4d demonstrate bias supply circuits for the
fully-synchronous push-pull topology. Biasing for full-
bridge schemes is identical to the push-pull circuits with
the obvious difference in the primary-side drive. In Figure
4a, the bias supply equals (VIN • N – VF). In Figure 4b and
4d, the bias supply equals (2 • VIN • N – VF). In Figure 4c
and 4e, the bias supply equals (VZ1 – VF).
In general, one of the simple, low-cost biasing schemes
suffices for LT4430 applications. However, design con-
straints such as a very wide input voltage range may force
employment of other biasing circuits. Other methods of
generating the bias supply may include an additional
transformer or output inductor winding, low-cost linear
regulators, discrete or monolithic charge pumps and buck/
boost regulators. However, if the bias supply gets this
complicated, a quick chat with your local LTC applications
engineer may result in a simpler solution.
•
•
•
•
VIN
4430 F04a
T1
1:N
VOUT
COUT
*OPTIONAL SEE TEXT
MF
L1
Q1
ME
Q2 LT4430
VBIAS
C1
R1*
D1
•
•
•
•
VIN
4430 F04b
T1
1:N
VOUT
COUT
*OPTIONAL SEE TEXT
MF
L1
Q1
ME
Q2
LT4430
VBIAS
C1
R1*
D1
Figure 4a. Typical Synchronous Push-Pull Converter
with Bias Generator
Figure 4b. Typical Synchronous Push-Pull Converter
with 2x Bias Generator
LT4430
15
4430fd
For more information www.linear.com/LT4430
applicaTions inForMaTion
Figure 4c. Typical Synchronous Push-Pull
Converter with Preregulator Bias
Figure 4d. Typical Synchronous
Push-Pull Current-Doubler Converter
with Bias Generator
Figure 4e. Typical Synchronous
Push-Pull Current-Doubler Converter
with Preregulator Bias
•
•
•
•
VIN
4430 F04c
T1
1:N
VOUT
LT4430
VBIAS
COUT
C1
R1*
D1
C2
*OPTIONAL SEE TEXT
MF
L1
Q1
ME
Q2
R3*
R2
QBS
Z1 •
•
•
•
VIN
4430 F04d
T1
1:N
VOUT
LT4430
VBIAS
COUT
C1
R1*
D1
ME
*OPTIONAL SEE TEXT
L2
Q2
MF
L1
Q1
•
•
•
•
VIN
4430 F04e
T1
1:N
VOUT
LT4430
VBIAS
COUT
C1
R1*
D1
C2
ME
*OPTIONAL SEE TEXT
L2
Q2
MF
L1
Q1
R3*
R2
QBS
Z1
LT4430
16
4430fd
For more information www.linear.com/LT4430
applicaTions inForMaTion
Figure 6a. Frequency Compensation with Opto-Coupler Common-Emitter Configuration
–
+
VCC
VREF VC
RC
CC
PRIMARY-SIDE
ERROR AMP
FB
ISOLATION
BARRIER
–
+
OPTO
DRIVER
OPTO
LT4430
COMP
1.1V
0.6V
–
+
ERROR
AMP
R3
R4
15k
R5
90k
4430 F06a
VOUT
FB
C3
R1
R2
C1
C2
RK
OPTO
CK
Figure 5. Setting Output Voltage
4430 F05
VOUT
75nA
FB
R2
R1
Setting Output Voltage
Figure 5 shows how to program the power supply output
voltage with a resistor divider feedback network. Connect
the top of R1 to VOUT, the tap point of R1/R2 to FB and
the bottom of R2 directly to GND of the LT4430. The FB
pin regulates to 600mV and has a typical input pin bias
current of 75nA flowing out of the pin.
The output voltage is set by the formula:
VOUT = 0.6V • (1 + R1/R2) – (75nA) • R1
Opto-Coupler Feedback and Frequency Compensation
An isolated power supply with good line and load regula-
tion generally employs the following strategy. Sense and
compare the output voltage with an accurate reference
potential. Amplify and feed back the error signal to the
supply’s control circuitry to correct the sensed error. Have
the error signal cross the isolation barrier if the control
circuitry resides on the primary-side. Coupling this signal
requires an element that withstands the isolation potentials
and still transfers the loop error signal.
Opto-couplers remain in prevalent use because of their
ability to couple DC signals. Opto-couplers typically con-
sist of an input infrared light emitting diode (LED) and an
output phototransistor separated by an insulating gap.
Most opto-coupler data sheets loosely specify the gain,
or current transfer ratio (CTR), between the input diode
and the output transistor. CTR is a strong function of the
input diode current, temperature and time (aging). Ag-
ing degrades the LED’s brightness and accelerates with
higher operating current. CTR variation directly affects the
overall system loop gain and the design must account for
total variation. To make an effective optical detector, the
output transistor design maximizes the base area to col-
lect light energy. This constraint yields a transistor with a
large collector-to-base capacitance. This capacitance can
influence the circuit’s performance based on the output
transistor’s hookup.
The two most common topologies for the output tran-
sistor of the opto-coupler are the common-emitter and
common-collector configurations. Figure 6a illustrates
the common-emitter design with the output transistor’s
collector connected to the output of the primary-side
controller’s error amplifier.
LT4430
17
4430fd
For more information www.linear.com/LT4430
applicaTions inForMaTion
Figure 6b. Frequency Compensation with Opto-Coupler Common-Collector Configuration
–
+
–
+
VCC
VREF
VC
RE
RK
PRIMARY-SIDE
ERROR AMP OPTO
DRIVER
OPTO
OPTO
LT4430
COMP
1.1V
0.6V
FB
–
+
ERROR
AMP
R3
R4
15k
R5
90k
4430 F06b
CK
ISOLATION
BARRIER VOUT
FB
C3
R1
R2
C1
C2
RC
CC
In this example, the error amplifier is typically a trans-
conductance amplifier with high output impedance and
RC dominates the impedance at the VC node. Frequency
compensation for this feedback loop is directly affected by
the output transistor’s collector-to-base capacitance as it
introduces a pole into the feedback loop. This pole varies
considerably with the transistor’s operating conditions. In
many cases, this pole limits the achievable loop bandwidth.
Cascoding the output transistor significantly reduces the
effects of this capacitance and increases achievable loop
bandwidth. However, not all designs have the voltage
headroom required for the cascode connection or can
tolerate the additional circuit complexity. The open loop
transfer function from the output voltage to the primary-
side error amplifier’s output is:
VC
VOUT
=
−A•
R2
R1+R2
⎛
⎝
⎜⎞
⎠
⎟•(1+s•R1•C1) •(1+s•R3 •C3)
[s •A•R1•(C2+C3)] •1+s•R3 •(C2 •C3)
(C2+C3)
⎛
⎝
⎜⎞
⎠
⎟
•
6•(1+s•RK•CK)
1+s•(RK•RD)
(RK+RD)
•CK
⎛
⎝
⎜⎞
⎠
⎟
•CTR •RC
(RK+RD)
•
1
1+s•rπ•(CTR •RC)
(RK+RD)
•CCB +CBE
⎡
⎣
⎢⎤
⎦
⎥
⎛
⎝
⎜⎞
⎠
⎟
•
1
(1+s•RC•CC)
where:
A = LT4430 open loop DC Gain
RD = Opto-coupler diode equivalent small-signal
resistance
CTR = Opto-coupler AC current transfer ratio
CCB = Opto-coupler nonlinear collector-to-base
capacitor
CBE = Opto-coupler nonlinear base-to-emitter
capacitor
rπ = Opto-coupler small-signal base-to-emitter
resistor
Figure 6a and its transfer function illustrate most of the
possible poles and zeroes that can be set and are shown
for the sake of completeness. In a practical application, the
transfer function simplifies considerably because not all
the poles and zeroes are used. Also, different combinations
of poles and zeroes can result in the same small signal
gain-phase characteristics but demonstrate dramatically
different large-signal behavior.
The common-collector configuration eliminates the miller
effect of the output transistor’s collector-to-base capaci-
tance and generally increases achievable loop bandwidth.
Figure 6b illustrates the common-collector design with the
output transistor’s emitter connected to the inverting input
of the primary-side controller’s error amplifier.
LT4430
18
4430fd
For more information www.linear.com/LT4430
applicaTions inForMaTion
In this example, the error amplifier is typically a voltage
error amplifier configured as a transimpedance amplifier.
The opto-coupler transistor’s emitter provides feedback
information directly to the FB pin and the resistor RE from
FB to GND sets the DC bias condition for the opto-coupler.
The open loop transfer function from the output voltage
to the primary-side error amplifier’s output is:
VC
VOUT
=
−A•
R2
R1+R2
⎛
⎝
⎜⎞
⎠
⎟•(1+s•R1•C1) •(1+s•R3 •C3)
[s •A•R1•(C2+C3)] •1+s•R3 •(C2 •C3)
(C2+C3)
⎛
⎝
⎜⎞
⎠
⎟
•
6•(1+s•RK•CK)
1+s•(RK•RD)
(RK+RD)
•CK
⎛
⎝
⎜⎞
⎠
⎟
•CTR •RC
(RK+RD)
•
1
1+s•rπ•CBE
( )
•1
(1+s•RC•CC)
Figure 6b and its transfer function illustrate most of the
possible poles and zeroes that can be set and are shown
for the sake of completeness. In a practical application,
the transfer function simplifies considerably because not
all the poles and zeroes are used.
In both configurations, the terms RD, CTR, rπ, CCB and CBE.
vary from part to part and also change with bias current.
For most opto-couplers, RD is 50Ω at a DC bias of 1mA,
and 25Ω at a DC bias of 2mA. CTR is the small signal AC
current transfer ratio. As an example, the Fairchild MOC207
opto-coupler has an AC CTR around 1, even though the
DC CTR is much lower when biased at 1mA or 2mA. Most
opto-coupler data sheets do not specify the terms CCB,
CBE and rπ and values must be obtained from empirical
measurements.
This frequency compensation discussion only addresses
the transfer function from the output back to the control
node on the primary-side. Compensation of the entire
feedback loop must combine this transfer function with
the transfer function of the power processing circuitry,
commonly referred to as the modulator. In an isolated
power supply, the modulator’s transfer function depends
on topology (flyback, forward, push-pull, bridge), current
or voltage mode control, operation in discontinuous or
continuous mode, input/output voltage, transformer turns
ratio and output load current. It is beyond this data sheet’s
scope to detail the transfer functions for all of the vari-
ous combinations. However, the power supply designer
must fully characterize and understand the modulator’s
transfer function to successfully frequency compensate
the feedback loop for all operating conditions.
Opto-Couplers
Opto-couplers are available in a wide variety of package
styles and performance criteria including isolation rating,
CTR, output transistor breakdown voltage, output transistor
current capability, and response time. Table 1 lists several
manufacturers of opto-coupler devices, although this is
by no means a complete list.
Table 1. Opto-Coupler Vendors
VENDOR PHONE URL
Agilent Technologies 800-235-0312 www.agilent.com
Fairchild Semiconductor 207-775-8100 www.fairchildsemi.com
Isocom 214-495-0755 www.isocom.com
Kodenshi Korea Corp. 82-63-839-2111 www.kodenshi.co.kr
NEC 81-44-435-1588 www.ncsd.necel.com
Sharp Microelectronics 877-343-2181 www.sharpsma.com
Toshiba 949-455-2000 www.toshiba.com
Vishay 402-563-6866 www.vishay.com
LT4430
19
4430fd
For more information www.linear.com/LT4430
applicaTions inForMaTion
Figure 7. Setting Overshoot Control Time
4430 F07
V
IN
OC
COC
IOC
8.5µA
Setting Overshoot Control Time
Figure 7 shows how to calculate the overshoot time by
connecting a capacitor from the OC pin to GND.
The overshoot control time, tOC, is set by the formula:
tOC = (COC • 0.6V)/8.5µA
The OC pin requires a minimum capacitor of 100pF due to
stability requirements with the overshoot control amplifier.
This yields a minimum time of 7µs which is generally on
the order of a few cycles of the switching regulator. Us-
ing the minimum capacitor value results in no influence
on start-up characteristics. Larger OC capacitor values
increase the overshoot control time and only increase the
amplifier stability. Do not modulate the overshoot control
time by externally increasing the OC charging current or
by externally driving the OC pin.
Choosing the Overshoot Control (OC) Capacitor Value
As discussed in the frequency compensation section,
the designer enjoys considerable freedom in setting the
feedback loop’s pole and zero locations for stability. Dif-
ferent pole and zero combinations can produce the same
gain-phase characteristics, but result in noticeably different
large-signal responses. Choosing frequency compensation
values that optimize both small-signal and large-signal
responses is difficult. Compromise values often result.
Power supply start-up and short-circuit recovery are the
worst-case large signal conditions. Input voltage and
output load characteristics heavily influence power supply
behavior as it attempts to bring the output voltage into
regulation. Frequency compensation values that provide
stable response under normal operating conditions can
allow severe output voltage overshoot to occur during
start-up and short-circuit recovery conditions. Large
overshoot often results in damage or destruction to the
load circuitry being powered, not a desirable trait.
The LT4430’s overshoot control circuitry plus one external
capacitor (COC) provide independent control of start-up
and short-circuit recovery response without compro-
mising small-signal frequency compensation. Choosing
the optimum COC value is a straightforward laboratory
procedure. The following description and set of pictures
explain this procedure.
Before choosing a value for the OC pin capacitor, complete
the remainder of the power supply design. This process
includes evaluating the chosen VIN bias generator topology
(please consult prior applications information section)
and optimizing frequency compensation under all normal
operating conditions. During this design phase, set COC
to its minimum value of 100pF. This ensures negligible
interaction from the overshoot control circuitry. Once these
steps are complete, construct a test setup that monitors
start-up and short-circuit recovery waveforms. Perform this
testing with the output lightly loaded. Light load, following
full slew operation, is the worst-case as the feedback loop
transitions from full to minimal power delivery.
As an example, refer to the schematic on the last page
illustrating the 5V, 2A isolated flyback converter. All of
the following photos are taken with VIN = 48V and ILD =
20mA. Figure 8a demonstrates the power supply start-up
and short-circuit recovery behavior with no overshoot
control compensation (COC = 100pF minimum). The 5V
output overshoots by several volts on both start-up and
short-circuit recovery due to the conservative nature of
the small-signal frequency compensation values.
LT4430
20
4430fd
For more information www.linear.com/LT4430
applicaTions inForMaTion
Next, increase COC’s value. Either use a capacitor substitu-
tion box or solder each new value into the circuit. Monitor
the start-up and short-circuit recovery waveforms. Note
any changes. Figures 8b to 8e illustrate what happens as
COC increases. In general, overshoot decreases as COC
increases.
COC = 0.0168µF in Figure 8b begins to affect loop dynam-
ics, but start-up still exhibits about 1.5V of overshoot.
Short-circuit recovery is considerably more damped. COC
= 0.022µF in Figure 8c damps start-up overshoot to 0.5V
and short-circuit recovery remains similar to that of Figure
8b. COC = 0.033µF in Figure 8d provides under 100mV
of overshoot and short-circuit recovery is slightly more
damped. COC = 0.047µF in Figure 8e achieves zero over-
shoot at the expense of additional damping and delay time
in short-circuit recovery. In this example, COC = 0.033µF
provides the best value for both start-up and short-circuit
recovery. Figure 8f provides an expanded scale of the
waveforms. After a COC value is selected, check start-up
and short-circuit recovery over the VIN supply range and
with higher output load conditions. Modify the value as
necessary.
Start-up and short-circuit recovery waveforms for various
designs will differ from the photos shown in this example.
Factors affecting these waveforms include the isolated
topology chosen, the primary-side and secondary-side
bias circuitry and input/output conditions. For instance,
in many isolated power supplies, a winding on the main
power transformer bootstraps the supply voltage for the
primary-side control circuitry. Under short-circuit condi-
tions, the primary-side control circuitry’s supply voltage
collapses, generating a restart cycle. Recovery from
short-circuit is therefore identical to start-up. In the flyback
example discussed, the primary-side control circuitry is
always active. Switching never stops in short-circuit. The
LT4430 error amplifier COMP pin changes from its low
clamp level to its higher regulating value during start-up
and changes from its high clamp level to its lower regulat-
ing point during short-circuit recovery. This large-signal
behavior explains the observed difference in the start-up
versus short-circuit recovery waveforms.
A final point of discussion involves the chosen COC value.
LTC recommends that the designer use a value that con-
trols overshoot to the acceptable level, but is not made
overly large. The temptation arises to use the overshoot
control function as a power supply “soft-start” feature.
Larger values of COC, above what is required to control
overshoot, do result in smaller dV/dt rates and longer
start-up times. However, large values of COC may stall the
feedback loop during start-up or short-circuit recovery,
resulting in an extended period of time that the output
voltage “flatspots”. This voltage shelf may occur at an
intermediate value of output voltage, promoting anomalous
behavior with the powered load circuitry. If this situation
occurs with the desired COC value, solutions may require
circuit modifications. In particular, bias supply holdup
times are a prime point of concern as switching stops
during these output voltage flatspots. As a reminder,
the purpose of this LT4430 circuitry is to control and
prevent excessive output voltage overshoot that would
otherwise induce damage or destruction, not to control
power supply timing, sequencing, etc. It is ultimately the
user’s responsibility to define the acceptance criteria for
any waveforms generated by the power supply relative to
overall system requirements.
LT4430
21
4430fd
For more information www.linear.com/LT4430
applicaTions inForMaTion
t = 5ms/DIV 4430 F08a
COC = 100pF
Figure 8a. Start-Up and Short-Circuit Recovery Waveforms
START-UP
VOUT
5V/DIV
SHORT-CIRCUIT
RECOVERY
VOUT
5V/DIV
t = 5ms/DIV 4430 F08b
COC = 0.0168µF = 0.01µF + 6.8nF
Figure 8b. Start-Up and Short-Circuit Recovery Waveforms
START-UP
VOUT
5V/DIV
SHORT-CIRCUIT
RECOVERY
VOUT
5V/DIV
t = 5ms/DIV 4430 F08c
COC = 0.022µF
Figure 8c. Start-Up and Short-Circuit Recovery Waveforms
START-UP
VOUT
5V/DIV
SHORT-CIRCUIT
RECOVERY
VOUT
5V/DIV
t = 5ms/DIV 4430 F08d
COC = 0.033µF
Figure 8d. Start-Up and Short-Circuit Recovery Waveforms
START-UP
VOUT
5V/DIV
SHORT-CIRCUIT
RECOVERY
VOUT
5V/DIV
t = 5ms/DIV 4430 F08e
COC = 0.047µF
Figure 8e. Start-Up and Short-Circuit Recovery Waveforms
START-UP
VOUT
5V/DIV
SHORT-CIRCUIT
RECOVERY
VOUT
5V/DIV
t = 5ms/DIV 4430 F08f
COC = 0.033µF
Figure 8f. Zoom In of Waveforms with Selected COC = 0.033µF
START-UP
VOUT
5V/DIV
SHORT-CIRCUIT
RECOVERY
VOUT
5V/DIV
LT4430
22
4430fd
For more information www.linear.com/LT4430
Typical applicaTions
•
•
•
•
36V TO 72V
V
IN
4430 TA03a
26V
8A
7, 10
PA0741
T1
8, 11
2
4
•
2
4
R24
261k
1%
R22
330Ω
R21
330Ω
C
OUT
= TDK
D1, D2, D7 = PHILIPS
Q1, Q2 = PHILIPS
L1 = PULSE ENGINEERING PB2020.103
T1 = PULSE ENGINEERING
T2 = COILCRAFT Q4470-B R23
8.2k
C15
2.2nFC13
1µF
R25
6.04k
1%
1
V
BS
V
BS
6
C
OUT
22µF
50V
X7R
2 5
3 4
NEC
PS2701
Q2
PH21NQ15
x2
Q1
BCX55
LT4430
ISOLATION
BARRIER
C4
1nF
C14
33nF
C16
10pF
VU1
Q4
PH20100
Q5
PH20100
D1
12V
VU1
R10
22k
R11
1.2k
R1
82k
R3
370k
R2
47k
R26
10Ω
C1
2.2µF
100V
C2
1µF
R14
0.008Ω
7
3
5LT1952
C3
2.2µF
VU1
4
14
15
13
16
SD_V
SEC
R
OSC
SS_MAXDC
SYNCNC
S
OUT
V
IN
9 8
BLANK GND
PGND
S
OUT
2 10
FB I
SENSE
1 11
COMP OC
6 12
V
REF
DELAY
D2
18V
D3
BAS516
V
BS
LTC3900
SYNC
8 7
TIMER
GND
6 2
CS
–
CS
–
V
CC
4 1
CS
+
FG
5 3
CG
V
IN
GND
OC
OPTO
COMP
FB
C11
1µF
C7
220pF
C17
2200pF
250V
R18
10k
L1
10µH
R19
10k
R17
10k
C12
1nF
R20
15k
V
BS
R15
2.2Ω
C10
1µF
R16
1k Q3
BCX55
D7
8.2V
C9
10nF
100V
D5
B0540W
D6
B0540W
C8
6.8nF
100V
R12
39k
R4
13.2k
R6
33k
R5
114k
R8
33k
R7
33k
R13
680Ω
R9
33k
D4
BAT760
C5
0.47µF
C6
0.1µF T2
200W, 26V, 95% Efficient Base Station Converter
LT4430
23
4430fd
For more information www.linear.com/LT4430
Typical applicaTions
5
46
AB
12V
VIN
15
LTC3723EGN-1
DRVB SDRB SDRA
COMP
CS
VCC
UVLO
9
150k
1
0.47µF
1µF
DRVA
DPRG VREF
SPRGGND SSFB CT
330pF
22nF
68nF
270pF
T2
1(1.5mH):0.5
T1
4T:6T(65µHMIN):6T:2T:2T
243k
604Ω
1%
11.5k
1%
750Ω
1.5k
813
3
L4
1mH
C3
68µF
20V
VF
•
•
3
2
8
1 9
5
4
16
10k
33k
200Ω
1/4W
R1
0.03Ω
1.5W
66.5k
RLEB
127 14
220pF
4.7nF
100Ω
1.1k
866Ω
1.5nF
464k
30k
1/4W
SYNC PVCC
CSF+
VF
LTC3901EGN
CSF–
8
11 12
1
4 10 13 7 1µF
1µF
4430 TA03b
–VOUT
VOUT
–VOUT
D7
10V
VOUT
MF MF2
GND PGND GND2 PGND2 TIMER
VCC
470pF
14 15
1k
1%
1k
1% 866Ω
42.2k
100Ω
1k
6.19k
1/4W
1%
6.19k
1/4W
1%
1k
1/4W
C1, C2
47µF
16V
x2
CSE+
VE
VF
VOUT
12V/20A
–VOUT
CSE–
6 5
ME ME2
2 3 16
Si7852DP
Si7370DP
x2
Si7370DP
x2
Si7852DP
L5
0.56µH
112
4
12V D5
D6
3
5
1
6
•
••
•
•
9
7
VE
+
0.1µF
Si7852DP
1
6
5
4
B
2
A
D3
D1
LTC4440ES6
BOOSTINP
TG
TSGND
VCC
12V
3
0.1µF
Si7852DP
1
6
5
42
B
D4
LTC4440ES6
BOOSTINP
TG
TSGND
VCC
12V
+VIN
VIN
–VIN
42V TO 56V 1µF
100V
+
1µF
1µF
100V
1µF, 100V TDK C3225X7R2A105M
C1, C2: SANYO 16TQC47M
C3: AVX TPSE686M020R0150
C4: MURATA GHM3045X7R222K-GC
D1: DIODES INC. ES1B
D3-D6: BAS21
D7: MMBZ5240B
L4: COILCRAFT DO1608C-105
L5: COILCRAFT DO1813P-561HC
L6: PULSE PA1294.132 OR
PANASONIC ETQP1H1R0BFA
R1, R2: IRC LRC2512-R03G
T1: PULSE PA0805.004
T2: PULSE PA0785
6
10
ISNS
ISNS
0.1µF
11
5
1
2
6
MOC207
C4
2.2nF
250V
470pF
1
2
3
VIN
GND
OPTO
5COMP
OC
4
FB
LT4430ES6
15nF
22nF
A
1.5k
22Ω
4.7Ω4.7Ω
R2
0.03Ω
1.5W
VE
1nF
100V
L6
1.25µH
10
1W
6
93
EFFICIENCY (%)
94
95
96
97
8 10 12
LOAD CURRENT (A)
14 16 18 20
42VIN
48VIN
56VIN
MMBT3904
•
1µF
100V
x3
1k
1/4W
LTC3723-1 240W 42VIN to 56VIN to 12V/20A Isolated 1/4 Brick (2.3" × 1.45")
LT4430
24
4430fd
For more information www.linear.com/LT4430
package DescripTion
1.50 – 1.75
(NOTE 4)
2.80 BSC
0.30 – 0.45
6 PLCS (NOTE 3)
DATUM ‘A’
0.09 – 0.20
(NOTE 3) S6 TSOT-23 0302
2.90 BSC
(NOTE 4)
0.95 BSC
1.90 BSC
0.80 – 0.90
1.00 MAX 0.01 – 0.10
0.20 BSC
0.30 – 0.50 REF
PIN ONE ID
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
3.85 MAX
0.62
MAX
0.95
REF
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
1.4 MIN
2.62 REF
1.22 REF
S6 Package
6-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1636)
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
LT4430
25
4430fd
For more information www.linear.com/LT4430
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
revision hisTory
REV DATE DESCRIPTION PAGE NUMBER
B 5/11 H-Grade and MP-Grade parts added. Reflected throughout the data sheet. 1-26
C 10/13 Corrected Q2 in Block Diagram from NPN to PNP.
Changed R24 from 26.1k to 261k.
8
22
D 7/15 Corrected typos in formulas. 17, 18
(Revision history begins at Rev B)
LT4430
26
4430fd
For more information www.linear.com/LT4430
LINEAR TECHNOLOGY CORPORATION 2004
LT 0715 REV D • PRINTED IN USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LT4430
relaTeD parTs
Typical applicaTion
PART NUMBER DESCRIPTION COMMENTS
LT1952/LT1952-1 Isolated Synchronous Forward Controllers Ideal for Medium Power 24V and 48V Input Applications
LTC3765/LTC3766 Isolated Synchronous No-Opto Forward Controller Chip Set Ideal for Medium Power 24V and 48V Input Applications
LTC3723-1/LTC3723-2 Synchronous Push-Pull and Full-Bridge Controllers High Efficiency with On-Chip MOSFET Drivers
LTC3721-1/LTC3721-2 Non-Synchronous Push-Pull and Full-Bridge Controllers Minimizes External Components, On-Chip MOSFET Drivers
LTC3722/LTC3722-2 Synchronous Isolated Full Bridge Controllers Ideal for High Power 24V and 48V Input Applications
LTC3900 Synchronous Rectifier Driver for Forward Converters Programmable Timeout, Synchronization Sequencer, Reverse
Inductor Current Sense
LTC3901 Synchronous Rectifier Driver for Push-Pull and Full-Bridge Programmable Timeout, Synchronization Sequencer, Reverse
Inductor Current Sense
LTC3803/LTC3803-3/
LTC3803-5
Flyback DC/DC Controller with Fixed 200kHz or 300kHz
Operating Frequency
VIN and VOUT Limited by External Components, 6-pin ThinSoT
Package
LTC3805/LTC3805-5 Adjustable Constant Frequency (70KHz to 700kHz) Frequency
Flyback DC/DC Controller
VIN and VOUT Limited by External Components, MSOP-10E and
3mm × 3mm DFN-10 Packages
LT3748 100V No Opto Flyback Controller 5V ≤ VIN ≤ 100V, Boundary Mode Operation, MSOP-16 with Extra
High Voltage Pin Spacing
LT3798 Off-Line Isolated No-Opto Flyback Controller with Active PFC VIN and VOUT Limited by External Components
5V, 2A Isolated Flyback Telecom Converter Start-Up Waveforms with Overshoot Control Implemented
•
•
36V TO 72V
VIN
–VIN
4430 TA02
5V
2A
9, 10
CTX-02-15242
T1
11, 12
2
4
R7
11k
1%
R10
680Ω
C1 = TDK, X7R
CO1, C02, C03 = TDK, X5R
D1, D2, D3 = PHILIPS
D4 = MICROSEMI
Q1 = FAIRCHILD
Q2 = DIODES, INC.
T1 = COOPER
MOC207 = FAIRCHILD
D5
MBR0530
R9
1k
C7
0.1µF
C5
1µF
R8
1500Ω
1%
VIN OPTO
CO3
100µF
6.3V
GND COMP
OC FB
MOC207
Q1
FDC2512
Q2
MMBTA42
LT4430
ISOLATION
BARRIER
C3
150pF
200V
C8
0.047µF
C6
0.033µF
C4
2200pF
250V
8.5V
CO2
100µF
6.3V
CO1
100µF
6.3V
D4
UPS840
D3
BAS516
D1
PDZ-9.1B
9.1V
8.5V
D2
BAS516
R6
470k
R5
6.8k
R1
220k
R2
100k
R4
220Ω
C2
1µF
10V
C1
1µF
100V
RCS
0.068Ω
R3
4.7k
ITH/RUN
ITH/SHDN NGATE
GND VCC
FB SENSE
LTC3803
