DS90LT012AHMF/NOPB - Texas Instruments

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DS90LT012AH

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SNLS199A –SEPTEMBER 2005–REVISED APRIL 2013

DS90LT012AH High Temperature 3V LVDS Differential Line Receiver

Check for Samples: DS90LT012AH

1FEATURES DESCRIPTION

The DS90LT012AH is a single CMOS differential line

2• -40 to +125°C Temperature Range Operation receiver designed for applications requiring ultra low

• Compatible with ANSI TIA/EIA-644-A Standard power dissipation, low noise, and high data rates.

• >400 Mbps (200 MHz) Switching Rates The devices are designed to support data rates in

excess of 400 Mbps (200 MHz) utilizing Low Voltage

• 100 ps Differential Skew (Typical) Differential Swing (LVDS) technology

• 3.5 ns Maximum Propagation Delay The DS90LT012AH accepts low voltage (350 mV

• Integrated Line Termination Resistor (100Ωtypical) differential input signals and translates them

typical) to 3V CMOS output levels. The DS90LT012AH

• Single 3.3V Power Supply Design (2.7V to 3.6V includes an input line termination resistor for point-to-

Range) point applications.

• Power Down High Impedance on LVDS Inputs The DS90LT012AH and companion LVDS line driver

• LVDS Inputs Accept LVDS/CML/LVPECL DS90LV011AH provide a new alternative to high

Signals power PECL/ECL devices for high speed interface

applications.

• Pinout Simplifies PCB Layout

• Low Power Dissipation (10mW Typical@ 3.3V

Static)

• SOT-23 5-Lead Package

Connection Diagram

Figure 1. Top View

See Package Number DBV (R-PDSO-G5)

Functional Diagram

Figure 2. DS90LT012AH

Truth Table

INPUTS OUTPUT

[IN+] −[IN−] TTL OUT

VID ≥0V H

VID ≤ −0.1V L

Full Fail-safe OPEN/SHORT or Terminated H

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Absolute Maximum Ratings (1)

Supply Voltage (VDD)−0.3V to +4V

Input Voltage (IN+, IN−)−0.3V to +3.9V

Output Voltage (TTL OUT) −0.3V to (VDD + 0.3V)

Output Short Circuit Current −100mA

Maximum Package Power Dissipation @ +25°C

DBV Package 902mW

Derate DBV Package 7.22 mW/°C above +25°C

Thermal resistance (θJA) 138.5°C/W

Storage Temperature Range −65°C to +150°C

Lead Temperature Range Soldering

(4 sec.) +260°C

Maximum Junction Temperature +150°C

ESD Ratings (2)

(1) “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be verified. They are not meant to imply

that the devices should be operated at these limits. Electrical Characteristics specifies conditions of device operation.

(2) ESD Ratings:

DS90LT012AH:

(a) HBM (1.5 kΩ, 100 pF) ≥2kV

(b) EIAJ (0Ω, 200 pF) ≥700V

(d) IEC direct (330Ω, 150 pF) ≥7kV

Recommended Operating Conditions Min Typ Max Units

Supply Voltage (VDD) +2.7 +3.3 +3.6 V

Operating Free Air

Temperature (TA)−40 25 +125 °C

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Electrical Characteristics

Over Supply Voltage and Operating Temperature ranges, unless otherwise specified. (1) (2)

Symbol Parameter Conditions Pin Min Typ Max Units

VTH Differential Input High Threshold VCM dependant on VDD(3) IN+, IN− −30 0 mV

VTL Differential Input Low Threshold −100 −30 mV

VCM Common-Mode Voltage VDD = 2.7V, VID = 100mV 0.05 2.35 V

VDD = 3.0V to 3.6V, VID = 100mV 0.05 VDD - 0.3V V

TA= 125°C 0.10 2.35 V

IIN Input Current (DS90LV012A) VIN = +2.8V VDD = 3.6V or 0V −10 ±1 +10 μA

VIN = 0V −10 ±1 +10 μA

VIN = +3.6V VDD = 0V −20 +20 μA

ΔIIN Change in Magnitude of IIN VIN = +2.8V VDD = 3.6V or 0V 4 μA

VIN = 0V 4 μA

VIN = +3.6V VDD = 0V 4 μA

IIND Differential Input Current VIN+ = +0.4V, VIN−= +0V 3 3.9 4.4 mA

VIN+ = +2.4V, VIN−= +2.0V

RTIntegrated Termination Resistor 100 Ω

CIN Input Capacitance IN+ = IN−= GND 3 pF

VOH Output High Voltage IOH =−0.4 mA, VID = +200 mV TTL OUT 2.4 3.1 V

IOH =−0.4 mA, Inputs terminated 2.4 3.1 V

IOH =−0.4 mA, Inputs shorted 2.4 3.1 V

VOL Output Low Voltage IOL = 2 mA, VID =−200 mV 0.3 0.5 V

IOS Output Short Circuit Current VOUT = 0V (4) −15 −50 −100 mA

VCL Input Clamp Voltage ICL =−18 mA −1.5 −0.7 V

IDD No Load Supply Current Inputs Open VDD 5.4 9 mA

(1) Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground

unless otherwise specified (such as VID).

(2) All typicals are given for: VDD = +3.3V and TA= +25°C.

(3) VDD is always higher than IN+ and IN−voltage. IN+ and IN−are allowed to have voltage range −0.05V to +2.35V when VDD = 2.7V and

|VID| / 2 to VDD −0.3V when VDD = 3.0V to 3.6V. VID is not allowed to be greater than 100 mV when VCM = 0.05V to 2.35V when VDD =

2.7V or when VCM = |VID| / 2 to VDD −0.3V when VDD = 3.0V to 3.6V.

(4) Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only. Only one output should be shorted

at a time, do not exceed maximum junction temperature specification.

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Switching Characteristics

Over Supply Voltage and Operating Temperature ranges, unless otherwise specified. (1) (2)

Symbol Parameter Conditions Min Typ Max Units

tPHLD Differential Propagation Delay High to Low CL= 15 pF 1.0 1.8 3.5 ns

VID = 200 mV

tPLHD Differential Propagation Delay Low to High 1.0 1.7 3.5 ns

(Figure 3 and Figure 4)

tSKD1 Differential Pulse Skew |tPHLD −tPLHD|(3) 0 100 400 ps

tSKD3 Differential Part to Part Skew (4) 0 0.3 1.0 ns

tSKD4 Differential Part to Part Skew (5) 0 0.4 1.5 ns

tTLH Rise Time 350 800 ps

tTHL Fall Time 175 800 ps

fMAX Maximum Operating Frequency (6) 200 250 MHz

(1) CLincludes probe and jig capacitance.

(2) Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO= 50Ω, trand tf(0% to 100%) ≤3 ns for IN±.

(3) tSKD1 is the magnitude difference in differential propagation delay time between the positive-going-edge and the negative-going-edge of

the same channel.

(4) tSKD3, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices

at the same VDD and within 5°C of each other within the operating temperature range.

(5) tSKD4, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices

over the recommended operating temperature and voltage ranges, and across process distribution. tSKD4 is defined as |Max −Min|

differential propagation delay.

(6) fMAX generator input conditions: tr= tf< 1 ns (0% to 100%), 50% duty cycle, differential (1.05V to 1.35 peak to peak). Output criteria:

60%/40% duty cycle, VOL (max 0.4V), VOH (min 2.4V), load = 15 pF (stray plus probes). The parameter is specified by design. The limit

is based on the statistical analysis of the device over the PVT range by the transition times (tTLH and tTHL).

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PARAMETER MEASUREMENT INFORMATION

Figure 3. Receiver Propagation Delay and Transition Time Test Circuit

Figure 4. Receiver Propagation Delay and Transition Time Waveforms

TYPICAL APPLICATIONS

Balanced System

Figure 5. Point-to-Point Application (DS90LT012AH)

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APPLICATION INFORMATION

General application guidelines and hints for LVDS drivers and receivers may be found in the following application

notes: LVDS Owner's Manual(SNLA187), AN-808(SNLA028), AN-977(SNLA166), AN-971(SNLA165), AN-

916(SNLA219), AN-805(SNOA233), AN-903(SNLA034).

LVDS drivers and receivers are intended to be primarily used in an uncomplicated point-to-point configuration as

is shown in Figure 5. This configuration provides a clean signaling environment for the fast edge rates of the

drivers. The receiver is connected to the driver through a balanced media which may be a standard twisted pair

cable, a parallel pair cable, or simply PCB traces. Typically the characteristic impedance of the media is in the

range of 100Ω. The internal termination resistor converts the driver output (current mode) into a voltage that is

detected by the receiver. Other configurations are possible such as a multi-receiver configuration, but the effects

of a mid-stream connector(s), cable stub(s), and other impedance discontinuities as well as ground shifting, noise

margin limits, and total termination loading must be taken into account.

The DS90LT012AH differential line receiver is capable of detecting signals as low as 100 mV, over a ±1V

common-mode range centered around +1.2V. This is related to the driver offset voltage which is typically +1.2V.

The driven signal is centered around this voltage and may shift ±1V around this center point. The ±1V shifting

may be the result of a ground potential difference between the driver's ground reference and the receiver's

ground reference, the common-mode effects of coupled noise, or a combination of the two. The AC parameters

of both receiver input pins are optimized for a recommended operating input voltage range of 0V to +2.4V

(measured from each pin to ground). The device will operate for receiver input voltages up to VDD, but exceeding

VDD will turn on the ESD protection circuitry which will clamp the bus voltages.

POWER DECOUPLING RECOMMENDATIONS

Bypass capacitors must be used on power pins. Use high frequency ceramic (surface mount is recommended)

0.1μF and 0.001μF capacitors in parallel at the power supply pin with the smallest value capacitor closest to the

device supply pin. Additional scattered capacitors over the printed circuit board will improve decoupling. Multiple

vias should be used to connect the decoupling capacitors to the power planes. A 10μF (35V) or greater solid

tantalum capacitor should be connected at the power entry point on the printed circuit board between the supply

and ground.

PC BOARD CONSIDERATIONS

Use at least 4 PCB board layers (top to bottom): LVDS signals, ground, power, TTL signals.

Isolate TTL signals from LVDS signals, otherwise the TTL signals may couple onto the LVDS lines. It is best to

put TTL and LVDS signals on different layers which are isolated by a power/ground plane(s).

Keep drivers and receivers as close to the (LVDS port side) connectors as possible.

DIFFERENTIAL TRACES

Use controlled impedance traces which match the differential impedance of your transmission medium (ie. cable)

and termination resistor. Run the differential pair trace lines as close together as possible as soon as they leave

the IC (stubs should be < 10mm long). This will help eliminate reflections and ensure noise is coupled as

common-mode. In fact, we have seen that differential signals which are 1mm apart radiate far less noise than

traces 3mm apart since magnetic field cancellation is much better with the closer traces. In addition, noise

induced on the differential lines is much more likely to appear as common-mode which is rejected by the

receiver.

Match electrical lengths between traces to reduce skew. Skew between the signals of a pair means a phase

difference between signals which destroys the magnetic field cancellation benefits of differential signals and EMI

will result! (Note that the velocity of propagation, v = c/E rwhere c (the speed of light) = 0.2997mm/ps or 0.0118

in/ps). Do not rely solely on the autoroute function for differential traces. Carefully review dimensions to match

differential impedance and provide isolation for the differential lines. Minimize the number of vias and other

discontinuities on the line.

Avoid 90° turns (these cause impedance discontinuities). Use arcs or 45° bevels.

Within a pair of traces, the distance between the two traces should be minimized to maintain common-mode

rejection of the receivers. On the printed circuit board, this distance should remain constant to avoid

discontinuities in differential impedance. Minor violations at connection points are allowable.

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TERMINATION

The DS90LT012AH integrates the terminating resistor for point-to-point applications. The resistor value will be

between 90Ωand 133Ω.

THRESHOLD

The LVDS Standard (ANSI/TIA/EIA-644-A) specifies a maximum threshold of ±100mV for the LVDS receiver.

The DS90LV012A and DS90LT012A support an enhanced threshold region of −100mV to 0V. This is useful for

fail-safe biasing. The threshold region is shown in the Voltage Transfer Curve (VTC) in Figure 6. The typical

DS90LT012AH LVDS receiver switches at about −30mV. Note that with VID = 0V, the output will be in a HIGH

state. With an external fail-safe bias of +25mV applied, the typical differential noise margin is now the difference

from the switch point to the bias point. In the example below, this would be 55mV of Differential Noise Margin

(+25mV −(−30mV)). With the enhanced threshold region of −100mV to 0V, this small external fail-safe biasing of

+25mV (with respect to 0V) gives a DNM of a comfortable 55mV. With the standard threshold region of ±100mV,

the external fail-safe biasing would need to be +25mV with respect to +100mV or +125mV, giving a DNM of

155mV which is stronger fail-safe biasing than is necessary for the DS90LT012AH. If more DNM is required, then

a stronger fail-safe bias point can be set by changing resistor values.

Figure 6. VTC of the DS90LT012AH LVDS Receiver

FAIL SAFE BIASING

External pull up and pull down resistors may be used to provide enough of an offset to enable an input failsafe

under open-circuit conditions. This configuration ties the positive LVDS input pin to VDD thru a pull up resistor

and the negative LVDS input pin is tied to GND by a pull down resistor. The pull up and pull down resistors

should be in the 5kΩto 15kΩrange to minimize loading and waveform distortion to the driver. The common-

mode bias point ideally should be set to approximately 1.2V (less than 1.75V) to be compatible with the internal

circuitry. Please refer to application note AN-1194, “Failsafe Biasing of LVDS Interfaces”(SNLA051) for more

information.

PROBING LVDS TRANSMISSION LINES

Always use high impedance (> 100kΩ), low capacitance (< 2 pF) scope probes with a wide bandwidth (1 GHz)

scope. Improper probing will give deceiving results.

CABLES AND CONNECTORS, GENERAL COMMENTS

When choosing cable and connectors for LVDS it is important to remember:

Use controlled impedance media. The cables and connectors you use should have a matched differential

impedance of about 100Ω. They should not introduce major impedance discontinuities.

Balanced cables (e.g. twisted pair) are usually better than unbalanced cables (ribbon cable, simple coax) for

noise reduction and signal quality. Balanced cables tend to generate less EMI due to field canceling effects and

also tend to pick up electromagnetic radiation a common-mode (not differential mode) noise which is rejected by

the receiver.

For cable distances < 0.5M, most cables can be made to work effectively. For distances 0.5M ≤d≤10M, CAT 3

(category 3) twisted pair cable works well, is readily available and relatively inexpensive.

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Pin Descriptions

Package Pin Number Pin Name Description

SOT-23

4 IN−Inverting receiver input pin

3 IN+ Non-inverting receiver input pin

5 TTL OUT Receiver output pin

1 VDD Power supply pin, +3.3V ± 0.3V

2 GND Ground pin

NC No connect

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SNLS199A –SEPTEMBER 2005–REVISED APRIL 2013

REVISION HISTORY

Changes from Original (April 2013) to Revision A Page

• Changed layout of National Data Sheet to TI format ............................................................................................................ 8

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PACKAGE OPTION ADDENDUM

www.ti.com 14-Feb-2018

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

DS90LT012AHMF NRND SOT-23 DBV 5 1000 TBD Call TI Call TI -40 to 125 N05

DS90LT012AHMF/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 N05

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

DS90LT012AHMF SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

DS90LT012AHMF/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

PACKAGE MATERIALS INFORMATION

www.ti.com 20-Dec-2016

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

DS90LT012AHMF SOT-23 DBV 5 1000 210.0 185.0 35.0

DS90LT012AHMF/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 20-Dec-2016

Pack Materials-Page 2

www.ti.com

PACKAGE OUTLINE

TYP

0.22

0.08

0.25

3.0

2.6

2X 0.95

1.9

1.45 MAX

TYP

0.15

0.00

5X 0.5

0.3

TYP

0.6

0.3

TYP

1.9

3.05

2.75

1.75

1.45

(1.1)

SOT-23 - 1.45 mm max heightDBV0005A

SMALL OUTLINE TRANSISTOR

4214839/C 04/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. Refernce JEDEC MO-178.

0.2 C A B

INDEX AREA

PIN 1

GAGE PLANE

SEATING PLANE

0.1 C

SCALE 4.000

www.ti.com

EXAMPLE BOARD LAYOUT

0.07 MAX

ARROUND 0.07 MIN

ARROUND

5X (1.1)

5X (0.6)

(2.6)

(1.9)

2X (0.95)

(R0.05) TYP

4214839/C 04/2017

SOT-23 - 1.45 mm max heightDBV0005A

SMALL OUTLINE TRANSISTOR

NOTES: (continued)

4. Publication IPC-7351 may have alternate designs.

5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

SYMM

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:15X

PKG

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

DEFINED

EXPOSED METAL

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

EXPOSED METAL

www.ti.com

EXAMPLE STENCIL DESIGN

(2.6)

(1.9)

2X(0.95)

5X (1.1)

5X (0.6)

(R0.05) TYP

SOT-23 - 1.45 mm max heightDBV0005A

SMALL OUTLINE TRANSISTOR

4214839/C 04/2017

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

7. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:15X

SYMM

PKG

www.ti.com

PACKAGE OUTLINE

TYP

0.22

0.08

0.25

3.0

2.6

2X 0.95

1.9

1.45 MAX

TYP

0.15

0.00

5X 0.5

0.3

TYP

0.6

0.3

TYP

1.9

3.05

2.75

1.75

1.45

(1.1)

SOT-23 - 1.45 mm max heightDBV0005A

SMALL OUTLINE TRANSISTOR

4214839/C 04/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. Refernce JEDEC MO-178.

0.2 C A B

INDEX AREA

PIN 1

GAGE PLANE

SEATING PLANE

0.1 C

SCALE 4.000

www.ti.com

EXAMPLE BOARD LAYOUT

0.07 MAX

ARROUND 0.07 MIN

ARROUND

5X (1.1)

5X (0.6)

(2.6)

(1.9)

2X (0.95)

(R0.05) TYP

4214839/C 04/2017

SOT-23 - 1.45 mm max heightDBV0005A

SMALL OUTLINE TRANSISTOR

NOTES: (continued)

4. Publication IPC-7351 may have alternate designs.

5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

SYMM

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:15X

PKG

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

DEFINED

EXPOSED METAL

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

EXPOSED METAL

www.ti.com

EXAMPLE STENCIL DESIGN

(2.6)

(1.9)

2X(0.95)

5X (1.1)

5X (0.6)

(R0.05) TYP

SOT-23 - 1.45 mm max heightDBV0005A

SMALL OUTLINE TRANSISTOR

4214839/C 04/2017

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

7. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:15X

SYMM

PKG

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including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to

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solely for this purpose and subject to the terms of this Notice.

TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI

products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections,

enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specifically

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Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that

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third party, or a license from TI under the patents or other intellectual property of TI.

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DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN

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and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements.

Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such

products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards

and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must

ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in

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Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life

support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all

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TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).

Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications

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Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s non-

compliance with the terms and provisions of this Notice.

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