PD69208M and PD69200 Datasheet 8-Port PSE PoE Manager and PSE PoE Controller Microsemi Corporate Headquarters One Enterprise, Aliso Viejo, CA 92656 USA Within the USA: +1 (800) 713-4113 Outside the USA: +1 (949) 380-6100 Fax: +1 (949) 215-4996 Email: sales.support@microsemi.com www.microsemi.com (c) 2015-2018 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of Microsemi Corporation. All other trademarks and service marks are the property of their respective owners. Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or the suitability of its products and services for any particular purpose, nor does Microsemi assume any liability whatsoever arising out of the application or use of any product or circuit. The products sold hereunder and any other products sold by Microsemi have been subject to limited testing and should not be used in conjunction with mission-critical equipment or applications. Any performance specifications are believed to be reliable but are not verified, and Buyer must conduct and complete all performance and other testing of the products, alone and together with, or installed in, any end-products. Buyer shall not rely on any data and performance specifications or parameters provided by Microsemi. It is the Buyer's responsibility to independently determine suitability of any products and to test and verify the same. The information provided by Microsemi hereunder is provided "as is, where is" and with all faults, and the entire risk associated with such information is entirely with the Buyer. Microsemi does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other IP rights, whether with regard to such information itself or anything described by such information. Information provided in this document is proprietary to Microsemi, and Microsemi reserves the right to make any changes to the information in this document or to any products and services at any time without notice. About Microsemi Microsemi Corporation (Nasdaq: MSCC) offers a comprehensive portfolio of semiconductor and system solutions for aerospace & defense, communications, data center and industrial markets. Products include high-performance and radiation-hardened analog mixed-signal integrated circuits, FPGAs, SoCs and ASICs; power management products; timing and synchronization devices and precise time solutions, setting the world's standard for time; voice processing devices; RF solutions; discrete components; enterprise storage and communication solutions, security technologies and scalable anti-tamper products; Ethernet solutions; Power-over-Ethernet ICs and midspans; as well as custom design capabilities and services. Microsemi is headquartered in Aliso Viejo, California, and has approximately 4,800 employees globally. Learn more at www.microsemi.com. PD-000303451. 5.0 11/18 Contents 1 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 Revision 5.0 Revision 4.0 Revision 3.0 Revision 2.0 Revision 1.2 Revision 1.1 Revision 1.0 ....................................................................... ....................................................................... ....................................................................... ....................................................................... ....................................................................... ....................................................................... ....................................................................... 1 1 1 1 2 2 2 2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 2.2 2.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Typical PoE Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Functional Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 Digital Block Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 PD Detection Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Classification Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Current Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Main Power MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Analog to Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Power on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 SPI Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.10.1 PD69208M SPI Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.10.2 Broadcast . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.10.3 PD69200 I2C Address Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.1 4.2 4.3 4.4 PD69200 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD69200 Features Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD69208M Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.1 Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.2 Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.3 Port Real Time Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.4 Port Current Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.5 Port Voltage Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.6 Main Voltage Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.7 Temperature Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.8 Digital Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.9 Immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD69208M Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 11 12 13 13 14 14 15 15 15 16 16 17 5 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1 5.2 Pin Configuration and Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.2.1 PD69200 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 iii 5.3 5.4 5.2.2 PD69208M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 PD69200 Recommended PCB Layout for 32 Pin QFN 5mm x 5mm . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 PD69208M Recommended PCB Layout for 56-Pin QFN 8mm x 8mm . . . . . . . . . . . . . . . . . . . . . . . . . 25 6 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.1 6.2 6.3 6.4 6.5 6.6 PD69200 Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 PD69208M Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 PD69208M Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Recommended Solder Reflow Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Tape and Reel--Packaging Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.5.1 PD69200 Tape and Reel Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.5.2 PD69208M Tape and Reel Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Reference Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 7.16 7.17 7.18 7.19 PD Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Legacy (Reduced Capacitor) Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port Start Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Over-Load Detection and Port Shut Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Disconnect Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IC Thermal Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Over-Temperature Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VMAIN Out of Range Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-Pair and 4-Pair Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port Power Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System OK Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port Matrix Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Good Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LED Stream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 37 37 38 38 38 38 38 38 39 39 39 39 39 39 39 39 40 40 8 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 iv Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Typical PoE Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 PD69208M Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 SPI Detailed Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 PD69200 Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 PD69208M Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 PD69200 Top-Layer Copper PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 PD69200 Top-Layer Solder Paste and Vias PCB Layout for Thermal Pad Array . . . . . . . . . . . . . 24 Top-Copper Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Top-Solder Paste Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Top-Layer Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 BOT and Internal Layers Copper Plane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Top-Layer Pin Geometry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 PD69200 Package Outline Drawing (32 Pin QFN 5 mm x 5 mm) . . . . . . . . . . . . . . . . . . . . . . . . . 29 PD69208M Package Drawing (56 Pin QFN 8 mm x 8 mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Classification Reflow Profiles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 PD69200 Tape Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 PD69200 Reel Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 PD69208M Tape and Reel Pin-1 Orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 PD69208M Tape Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 PD69208M Reel Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4-Pair PoE System Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Typical IEEE802.3at Port PoE Voltage Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 v Tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 SPI Communication - Packet Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 PD69208M SPI Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 PD69208M Broadcast . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 SPI Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 I2C Address Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 PD69200 Features Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 PD69208M Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 PD69208M Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 PD69208M Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 PD69208M Port Real Time Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 PD69208M Port Current Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 PD69208M Port Voltage Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 PD69208M Main Voltage Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 PD69208M Temperature Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 PD69208M Digital Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 PD69208M Immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 PD69200 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 PD69208M Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 PD69200 Package Outline Dimensions and Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 PD69208MPackage Outline Dimensions and Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 PD69208M Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 PD69200 Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Classification Reflow Profiles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Pb-Free Process - Package Classification Reflow Temperatures . . . . . . . . . . . . . . . . . . . . . . . . . 32 PD69200 Tape Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 PD69200 Reel Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 PD69208M Tape Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 PD69208M Reel Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 PD69208M Manufacturing and Ordering Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 vi Revision History 1 Revision History The revision history describes the changes that were implemented in the document. The changes are listed by revision, starting with the most current publication. 1.1 Revision 5.0 Revision 5.0 of this document was published in November 2018. The following was a summary of the changes made in this revision: * * * * * * * * * * 1.2 Updated the Features and Applications details. For more information, see Features, page 4 and Applications, page 4. Port real time protection details are updated for IPORT, ILIM, ICUT, IUDL, PPWR, and TMPS. For more information, see Table 10, page 14. Port current monitoring information is updated for accuracy. For more information, see Table 11, page 14. Main voltage information is updated for accuracy. For more information, see Table 13, page 15. The PD69200 pin diagram is updated. For more information, see Figure 4, page 18. The Top-Layer Pin Geometry measurement is updated. For more information, see Figure 12, page 28. The PD692000 Thermal Specifications table is added. For more information, see Table 23, page 31. The company name Freescale is replaced with NXP across the document. Updated Figures 8 - 12. For more information, see Figure 8, page 25,Figure 9, page 26, Figure 10, page 27, Figure 11, page 27, and Figure 12, page 28. Added table footnotes for D, VVVV, and SS. For more information, see the Ordering Information, page 41. Revision 4.0 Revision 4.0 of this document was published in February 2018. The following was a summary of the changes: * * * * * 1.3 Preliminary designation was removed. Thermal specifications were updated. For more information, see PD69200 Thermal Specifications, page 31. The tape specification was updated. For more information, see Figure 19, page 35. Tape mechanical data was added. For more information, see Table 28, page 35. Ordering part numbers were updated. For more information, see Ordering Information, page 41. Revision 3.0 Revision 3.0 of this document was published in November 2017. The following was a summary of the changes: * * * * * * 1.4 Maximum storage temperature value is no longer preliminary. The link to stencil and via plug recommendations was updated. Application information was updated. Maximum slew rate requirement of 100 mS was added. Manufacturing and ordering part number information was updated. Updated revision 2.0 history to include entry for the redefinition of quiescent current in terms of port threshold. Revision 2.0 Revision 2.0 of this document was published in September 2017. The following was a summary of the changes: * * * Updated the recommended PCB layout for better manufacturability. Redefined quiescent current in terms of port threshold. Added the PD69208M Manufacturing and Ordering Part Numbers table. Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 1 Revision History * * * * * * * * * * * * * 1.5 Added a note about I2C communication configuration. Added table footnotes for ESD (HBM and CDM). Updated the main voltage monitoring table for accuracy data. Updated the Peak Classification Temperature (TP). Updated the description for pin 24 for PD69200. Updated the description for pin 19 for PD69208M. Updated the thermal specifications table. Changed the notation from VPORT_NEGx to VPORT. Added a footnote for Absolute Storage Temperature in the table. Updated the accuracy values in the Port Current Monitoring table. Updated the RSIG_LOW and RSIG_HIGH values in the Detection table. Updated the LSB value in the Temperature Monitoring table. Updated the values for D11, D12, D15, D16, and D17 in the SPI Timing Diagram Description table. Revision 1.2 Revision 1.2 of this document was published in August 2016. The following is a summary of the changes: * * * 1.6 According to PCN155881, qualification of UTAC Thailand assembly for PD6920X. Parts from UTAC will be identified by different marking that was added. Match 802.3af ILIM and IINRUSH levels to IEEE standard levels. Match 802.3at ILIM low level to IEEE standard levels. Revision 1.1 Revision 1.1 of this document was published in July 2016. The following is a summary of the changes: * * 1.7 Updated the feature's list. Changed MSL1 of PD69208 to MSL3. Updated ordering information. Changed MSL1 of PD69208 to MSL3. Revision 1.0 Revision 1.0 of this document was published in December 2015. This was the first publication. Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 2 Overview 2 Overview Microsemi's PD69208M Power over Ethernet (PoE) manager IC integrates power, analog, and state-ofthe-art logic into a single 56-pin, plastic QFN package. The device is used in Ethernet switches and Midspans to allow network devices to share power and data over the same cable. The PD69208M device is an 8-port, mixed-signal, and high-voltage PoE driver. Together with the PD69200 external MCU, it performs as a PSE system. Microsemi's PoE controller, PD69200, is a cost-effective, pre-programmed MCU designed to implement enhanced mode. PD69208M/PD69200 chip-set supports PoE Powered Device (PD) detection, power-up, and protection according to IEEE standards, as well as legacy/pre-standard PD detection. It provides PD real-time protection through the following mechanisms: overload, under-load, over-voltage, over-temperature, and short-circuit, and enables operation in a standalone mode. It also executes all real-time functions as specified in IEEE802.3at and IEEE802.3bt Class 3. PD69208M supports supply voltages between 32 V and 57 V without additional power supply sources. A system that powers over four pairs can be implemented by combining two ports of PD69208M, enabling an extra feature for a simple and low-cost, high-power PD device. An on-going monitoring of system parameters for the host software is available via communication. Internal thermal protection is implemented in the chip. PD69208M is a low-power dissipation device that uses internal MOSFETs and internal 100 m sense resistors. PD69200 features an ESPI bus for all PD69208M. It is developed based on NXP Kinetis_L family, MKL15Z128VFM4, that is embedded with the ARM CortexTM-M0+ core. It also uses I2C or UART interface to the host CPU, and is designed to support software field upgradable through the communication interface. PD69208M is available in a 56 pin, 8 mm x 8 mm QFN package. PD69200 is available in 32 pin, 5 mm x 5 mm QFN package. Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 3 Overview 2.1 Features * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 2.2 8 independent channels Complies with IEEE802.3af-2003, IEEE802.3at-2009 (including two-event classification), and IEEE802.3bt Drives 2-pair power ports or 4-pair ports Supports pre-standard PD detection Single DC voltage input (32 V to 57 V) Built in 3.3 V and 5 V regulators Input voltage out of range protection Wide ambient temperature range: -40 C to +85 C On-chip Over-temperature thermal protection and monitoring Low power dissipation (0.1 sense resistor and 0.2 MOSFET Rdson per channel) Includes Reset command pin 4 x direct address configuration pins Continuous port monitoring and system data Configurable load current setting Configurable PSE AT/AF/BT-Type3 modes Power soft start mechanism Voltage monitoring/protection Internal power on reset Emergency power management supporting four configurable power bank I/Os Advance System Power Management algorithm supports up to 96 physical ports Can be cascaded to up to 12 PoE devices (96 ports) Supports both UART and I2C interfaces to host CPU Backwards compatible with Microsemi communication protocol used at prior generations LED stream support System OK indication Software download via I2C or UART Detailed port status Programmable threshold temperature alarm limit Interrupt out pin for system and port events Forced port power ON function Port power limit setting Port matrix and priority Automatic PoE device type detection MSL3, RoHS compliant Applications * * * * * Power over Ethernet (all IEEE compliant 2-pair modes) Supports 4-pair and IEEE802.3bt PSE Type 3 Switches/Routers/Midspans Industrial automation PoE for LED lighting Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 4 Overview 2.3 Typical PoE Application The following figure illustrates the typical PoE application of PD69208M and PD69200 devices. Figure 1 * Typical PoE Application 90$,1 )6\VWHP &DSDFLWRU 9B,62 ) 9B,62 [5(6(7B,1 9''$ )9 90$,1 9'' 3RZHU6XSSO\ 0RQLWRULQJ 9$8; 9$8;3 8$57B7; 8$57B5; ,&,QWHUIDFH 1R,VRODWLRQ5HTXLUHG ,&B6&/ 6&. ,&B6'$ 6&. [&6 [&6 90$,1 Q) 9 3257B1(* 3257B1(* 3*'! 8$57,QWHUIDFH 1R,VRODWLRQ5HTXLUHG $'$5:= 026, 9B,62 . 9 ) 9 9 ) ) . 0,62 3' 90$,1 026, Q) 9 3257B1(* 3'0 3R(0DQDJHU 0,62 3R(&RQWUROOHU [',6$%/(B32576 3257B1(* ,VRODWLRQ [,17B287 9B,62 [/('B&6 [/('B2( [/('B/$7&+ 2SWLRQDO/('V%XIIHUV &RQWURO:LWK63,%86 8$57,&$GGUHVV ,5() 966$ 966 '*1' $*1' . ) Note: Fuses per port are not required for use in circuits with total power level of up to 3kW as the PD69208M designed to fulfill limited power source (LPS) requirements per the latest editions of IEC60950-1 and EN60950-1. Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 5 Functional Descriptions 3 Functional Descriptions The following illustration shows the functional blocks of PD69208M. Figure 2 * PD69208M Block Diagram 3'0 &ODVV8'/0RQLWRU &XUUHQW/LPLWHU 3RZHU026)(7 &ODVV8'/0RQLWRU /LQH'HWHFWLRQ &XUUHQW*HQHUDWRU 3RZHU026)(7 &XUUHQW/LPLWHU &ODVV8'/0RQLWRU &XUUHQW/LPLWHU /LQH'HWHFWLRQ &XUUHQW*HQHUDWRU &ODVV8'/0RQLWRU /LQH'HWHFWLRQ &XUUHQW*HQHUDWRU /HYHO 6KLIWHU 3RZHU026)(7 &XUUHQW/LPLWHU 3RZHU026)(7 3RZHU026)(7 3RZHU026)(7 3RZHU026)(7 3RZHU026)(7 Q) 93257B1(* &XUUHQW/LPLWHU &ODVVLILFDWLRQ 9ROWDJH5HJXODWRU &ODVV8'/0RQLWRU &ODVV 5HIHUHQFH /LQH'HWHFWLRQ &XUUHQW*HQHUDWRU 93257B1(* 9PDLQ 3RUW)URQW(QG 7HPSHUDWXUH0HDVXUHPHQW Q) Q) 3RUW)URQW(QG 3RUW)URQW(QG 9PDLQ 9PDLQ 93257B1(* &XUUHQW/LPLWHU 0DLQ 9ROWDJH0HDVXUHPHQW 93257B1(* &XUUHQW/LPLWHU &XUUHQW 0XOWLSOLHU 3RUW 9ROWDJH0HDVXUHPHQW &XUUHQW/LPLWHU ELW$'& Q) 3RUW)URQW(QG /LQH'HWHFWLRQ &XUUHQW*HQHUDWRU 93257B1(* $QDORJ,QWHUIDFH 9PDLQ 0,6& &ODVV8'/0RQLWRU Q) $'& &RQWUROOHU 9&0 3RUW&XUUHQW0HDVXUHPHQW 3RUW)URQW(QG 9PDLQ 5HDO7LPH 3URWHFWLRQ 573 /LQH'HWHFWLRQ &XUUHQW*HQHUDWRU 93257B1(* 5HJLVWHUV 0DS &ODVV8'/0RQLWRU Q) 2VFLOODWRU %DQG*DS 'LJLWDO%ORFN 63, 6ODYH 3RUW)URQW(QG 9PDLQ 325 /LQH'HWHFWLRQ &XUUHQW*HQHUDWRU 93257B1(* 9ROWDJH 5HJXODWRU 3RUW)URQW(QG &ODVV8'/0RQLWRU Q) /LQH'HWHFWLRQ &XUUHQW*HQHUDWRU 3RUW)URQW(QG 9PDLQ 9PDLQ Q) 93257B1(* The following sections describe the functional blocks of PD69208M. 3.1 Digital Block Module The logic main control block includes digital timing mechanisms and state machines synchronizing and activating PoE functions according to PD69200 control commands, such as: * * * * * * * * * 3.2 Real Time Protection (RTP) Start Up Macro (DVDT) Load Signature Detection (RES DET) Classification Macro (CLASS) Voltage and Current Monitoring (VCM) ADC Interfacing Direct Digital Signals with Analog Block SPI Communication Block Registers PD Detection Generator Upon request from PD69200 to the main control module, the PD detection generator generates four different voltage levels to ensure a robust AF/AT/BT PD detection functionality. 3.3 Classification Generator Upon request from PD69200 to the main control module, state machine applies a regulated class event and mark event voltage to ports, as required by IEEE standards. Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 6 Functional Descriptions 3.4 Current Limiter This circuit continuously monitors the current of powered ports and limits the current to a pre-defined value set by AF/AT. When the current value exceeds this specific value, the system starts measuring the elapsed timing. If this interval is greater than a preset threshold, the port is disconnected. 3.5 Main Power MOSFET The main power switching FET is used to control PoE current into load. 3.6 Analog to Digital Converter A 10-bit analog to digital converter (ADC) is used to convert analog signals into digital registers for the logic control module. 3.7 Power on Reset Power on Reset (PoR) monitors the internal 3.3 V and 5 V DC levels. If this voltage drops below specific thresholds, a reset signal is generated, and PD69208M is reset. 3.8 Voltage Regulator The voltage regulator generates 3.3 V and 5 V for internal circuitry. These voltages are derived from VMAIN supply. To use internal voltage regulator connect: * * VAUX5 to DRV_VAUX5 VAUX3P3 to VAUX3P3_INT There are three options to reduce PD69208M power dissipation by regulating voltage outside the chip: * * * Use an external NPN transistor to regulate the 5 V. In this setup, the configuration of regulators pins should be as follows: * DRV_VAUX5 is connected to NPN BASE * VAUX5 is connected to NPN EMITTER (Connect Collector to VMAIN) * VAUX3P3 is connected to VAUX3P3_INT Supply PD69208M with an external 5 V voltage regulator. In this setup, regulators pins configuration should be as follows: * VAUX3P3 is connected to VAUX3P3_INT * DRV_VAUX5 is not connected (left open) * VAUX5 is connected to external 5 V Supply PD69208M with an external 3.3 V voltage regulator. In this setup, regulators pins configuration should be as follows: * VAUX5 is connected to DRV_VAUX5 * VAUX3P3_INT is not connected (left open) * VAUX3P3 is connected to external 3.3 V These options can be implemented simultaneously to reduce PD69208M power dissipation. 3.9 Clock PD69208M clock (CLK) is an internal 8 MHz clock oscillator. Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 7 Functional Descriptions 3.10 SPI Communication PD69208M uses SPI communication in SPI slave mode to communicate with PD69200 MCU. Each PD69208M has an address determined by ADDR0-ADDR3 pins. The PD69200 can support up to 12 ICs. The actual frequency between PD69200 and PD69208M ICs is 1 MHz. The following table lists the SPI communication packet structure. Table 1 * SPI Communication - Packet Structure Control byte Selects PD69208M According to the address R/W Bit Internal Register Address Data Written to IC (in write access) Number of words Read from IC (in (only in read access) read access) 8 bits R(0)/W(1) 8 bits 8 bits 3.10.1 16 bits PD69208M SPI Addressing PD69208M operates in 8-bit address and 16-bit data. It responds to SPI transaction if the first SPI byte (IC address byte bits[7:1]) complies with the following: Table 2 * 3.10.2 PD69208M SPI Addressing 3 Bits (bit 7:5) 4 Bits (bit 4:1) 1 Bit (bit 0) 000 Address Input Pin Read/Write Broadcast * * A broadcast command is intended to instruct all connected PD69208M ICs to perform a specific operation. The broadcast command is a write command with the standard packet structure. In a broadcast read operation, the read data is not valid and the read operation has no impact. Table 3 * PD69208M Broadcast 3 Bits (bit 7:5) 4 Bits (bit 4:1) 1 Bit (bit 0) 001 0000 Write Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 8 Functional Descriptions Figure 3 * SPI Detailed Timing Diagram SPI1 frame 8 SCK clock cycles D3 D1 D2 D6 Noise Spike D14 8 SCK clock cycles 8 SCK clock cycles D5 D7 D2 D8 D4 D13 CS_N SCK D9 D10 MOSI D15 D12 D11 MISO The following table lists the SPI timing diagram description. Table 4 * SPI Timing Description Name Min Delay Max Delay Description D1 910 nS D2 45 % D3 340 nS SPI_CS setup to SPI clock positive edge (delay after SPI_CS active signal) D4 340 nS SPI_CS hold to SPI clock positive edge (delay before SPI_CS inactive signal) D5 2 SPI clock cycles Delay between last SCK in eSPI1 frame and first SCK at adjacent eSPI1 frame D6 1 SPI clock cycles Between byte 0 (IC address) and byte 1 (address) D7 1 SPI clock cycles Between byte 1 (address) and byte 2 (data). D8 1 SPI clock cycles Between byte 2 (MS data byte) and byte 3 (LS data byte). D9 340 nS MOSI setup time D10 340 nS MOSI hold time SPI clock period 55% SPI duty cycle D11 700 nS MISO tri-state to valid data from clock positive edge D12 700 nS MISO valid data to tri-state from SPI_CS positive edge D13 1 SPI clock cycles SPI_CS width (Delay eSPI1 frame to adjacent eSPI1 frame) D14 60 nS Filtered glitch width D15 D3 + D11 + 24 SPI clock MISO tri-state from SPI_CS negative edge to valid data cycles D16 200 nS MISO setup to SCK positive edge D17 200 nS MISO hold to SCK positive edge Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 9 Functional Descriptions 3.10.3 PD69200 I2C Address Selection The I2C interface between the host CPU and a specific PD69200 requires setting the PD69200 address. This is done by applying a specific voltage level to pin #22 (I2C_ADDR_MEAS) as listed in the following table: Table 5 * I2C Address Selection I2C_ADDR Voltage Level I2C Address (Hexadecimal) 0.00 to 0.21 VDC UART 0.21 to 0.41 VDC 0x4 0.41 to 0.62 VDC 0x8 0.62 to 0.83 VDC 0xC 0.83 to 1.03 VDC 0x10 1.03 to 1.24 VDC 0x14 1.24 to 1.44 VDC 0x18 1.44 to 1.65 VDC 0x1C 1.65 to 1.86 VDC 0x20 1.86 to 2.06 VDC 0x24 2.06 to 2.27 VDC 0x28 2.27 to 2.48 VDC 0x2C 2.48 to 2.68 VDC 0x30 2.68 to 2.89 VDC 0x34 2.89 to 3.09 VDC 0x38 3.09 to 3.30 VDC 0x3C Note: UART communications configuration: * * * * * Bits per second: 19,200 bps Data bits: 8 Parity: None Stop bits: 1 Flow control: None Note: I2C communication configuration: * * * Address: 7 bits Clock stretch: host should support Transaction: 15 bytes or 1 byte Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 10 Electrical Specifications 4 Electrical Specifications The following sections describes the electrical characteristics of PD69200 and PD69208M devices. 4.1 PD69200 Electrical Characteristics In this application, PD69200 consumption is ~20mA. * * * 4.2 Manufacturer: NXP Manufacturer part number: MKL15Z128VFM4 Maximum pull-ups consumption based on PD69200 application is 2mA. See the hardware application note document: catalog number PD69208_AN_211 PD69200 Features Description The following table lists the main features of PD69200. Table 6 * PD69200 Features Description Features Description Supports up to 12 PoE devices 96 physical ports (48 logical) Up to 12 PoE devices can be cascaded, fitting into a 96-physical-port PoE system that uses one PoE controller (PD69200). PD69200 can support up to 48 logical ports. A logical port can be built from 2xPhysical ports or 1xPhysical port. Power Management The system supports three power management modes: Class (LLDP), Dynamic and Static. Threshold Configuration Over-voltage and under-voltage thresholds can be configured for disconnection purposes. High Power Ports (2 pairs or 4 pairs) PoE devices can be configured (both hardware and software) to enable higher current through ports (up to ~627 mA) or double power at the RJ in case of 4 pairs. Communication Supports both I2C and UART interfaces with the host CPU. Legacy (reduced capacitance) Detection Enables detection and powering of pre-standard devices (PDs) up to 30 F. LED Stream Provides a direct SPI interface to an external LED stream circuitry. Enables designers to implement a simple LED circuit that does not require a software code. (LED stream clock frequency is 1 MHz). System OK Indication Provides a digital output pin to host. System validity indication, when the system OK pin state is low. The output behavior is controlled by software mask register settings (Mask 0x28). The mask default settings is 0, meaning that this pin indicates valid software and Vmain is within the range. This pin is active low. For more information, see the Serial Communication Protocol User Guide document - Catalog Number: PD69200_UG_COMM_PROT). System and Port Measurements Measurements of the following parameters: Current (mA), Power Consumption (W), Vmain (V), Port Voltage (V), and PD Class (0-4). Detailed Port Status Port statuses are received from PoE managers. Statuses such as port on and port off due to disconnection or overload. Interrupt Pin Interrupt out from PoE controller, PD69200, indicating events such as: port on, port off, port fault, PoE device fault, voltage out of range, and more. For a full list of interrupt events, see the Serial Communication Protocol User Guide document - Catalog Number: PD69200_UG_COMM_PROT. Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 11 Electrical Specifications Table 6 * PD69200 Features Description (continued) Features Description Port Power Limit Configurable port power limit; when a port exceeds the limit, it is automatically disconnected. Port Matrix Control Enables layout designers to connect any physical port to any logical port as required. 'Power Good' Interrupt from Power For systems comprising more than a single power supply, when one power Supply directly to PoE Drivers. supply fails, a fast port disconnection mechanism is executed to maintain operation and prevent collapse of other power supplies. 4.3 PD69208M Electrical Characteristics Unless otherwise specified under conditions, the Min and Max ratings stated in the following table apply to the entire specified operating ratings of the device. Typ values stated are either by design or by production testing at 25 C ambient. Table 7 * PD69208M Electrical Characteristics Symbol Parameter Conditions Min VMAIN Main Supply Voltage Supports Full IEEE802.3AF and AT functionality VPORT Port Output VMAIN- VPORT_NEGx VTH POR Threshold Internal or External 3.3 V supply 8 V Main Power Supply Current @ Operating Mode.VMAIN = 55 V 14 mA IMAIN Typ Max Units 32 57 V 0 57 V VAUX5 5 V Output Voltage VAUX5-AGND 4.5 5 5.5 V VAUX3P3 3.3 V Output Voltage VAUX3P3-AGND 3 3.3 3.6 V IAUX3P3 3.3 V Output Current for application use Without external NPN 5 mA With external NPN transistor on VAUX5 30 mA VAUX3P3_IN 3.3 V Input Voltage VAUX3P3-AGND DVDD 3 3.3 3.6 V Digital 3.3 V Input Voltage DVDD-DGND 3 3.3 3.6 V PORTP Power On Reset DVDD Trip Point DVDD-DGND 2.575 2.775 2.975 V PORHYS Power On Reset DVDD Hysteresis PORTP-DGND 0.2 0.25 0.3 V RCH_ON Total Channel Resistance Rds_on + Rsense + Rbonding 0.34 Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 12 Electrical Specifications 4.3.1 Detection Table 8 * PD69208M Detection Symbol Parameter Conditions VOC Pre-detection Voltage, Open-circuit Voltage VVALID Max Units VMAIN- VPORT_NEGx, open port 7.8 V Detection Voltage VMAIN- VPORT_NEGx, for IEEE802.3 compliant signature resistance (RSIG < 33 K) 9.3 V ISC Short Circuit Current VMAIN- VPORT_NEGx = 0 V 408 A RSIG_LOW Minimum Valid Detection Resistance 15 19 K RSIG_HIGH Maximum Valid Detection Resistance 26.5 33 K 4.3.2 Classification Table 9 * PD69208M Classification Symbol Parameter VCLASS Conditions Min Typ 388 Min Typ Max Units Class Event Output Voltage VMAIN- VPORT_NEGx; 0 mA IPORT 50 mA 15.5 18 20.5 V VMARK Mark Event Output Voltage VMAIN- VPORT_NEGx; 0.1mA IPORT 5 mA 7 8.5 10 V ICLASS_LIM Class event current limitation VMAIN- VPORT_NEGx = 0 V 51 70 100 mA IMARK_ LIM Mark event current limitation VMAIN- VPORT_NEGx= 0 V 51 70 100 mA Classification Current Thresholds Class 0 0 5 mA Class 1 8 13 mA Class 2 16 21 mA Class 3 25 31 mA Class 4 35 45 mA Class Error 51 100 mA Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 13 Electrical Specifications 4.3.3 Port Real Time Protection Table 10 * PD69208M Port Real Time Protection Symbol Parameter Conditions Min TRISE Turn on rise time From 10% to 90% of the voltage difference at the VPORT_NEGx in POWER_ON state from the beginning of POWER_UP 15 IINRUSH Output current in POWER_UP state CLOAD 180 F1 400 TINRUSH Inrush Time IPORT Output Operating Current ICUT Overload Current TCUT Overload Time Limit ILIM Port Current Limit Typ Max Units S 425 450 mA 65 mS 802.3af 10 360 mA 802.3at 10 627 mA 802.3bt class 5 10 560 mA 802.3bt class 6 10 692 mA 802.3af 375 mA 802.3at 645 mA 802.3bt class 5 589 mA 802.3bt class 6 709 mA 62 64 66 mS 802.3af 400 425 450 mA 802.3bt class 1-3 670 720 770 mA 802.3at, 802.3bt class 4-6 790 850 892 1 2 3 mS 2 % TLIM Port Current Limit Time VMAIN- VPORT_NEGx< 30 V PPWR Port power accuracy > 90 W IUDL DC Disconnect Under-load Current 2 Pairs 6 7.5 9 mA 4 Pairs (for each pairset) 2 2.5 3 mA 322 324 326 mS 50 mS TMPDO PD Maintain Power Signature Dropout Time Limit TMPS PD Maintain Power Signature Time For Validity 802.3bt PSE Type 1, 2 46 48 802.3bt PSE Type 3, 4 3 4 TOFF Turn Off Time From VMAIN to 2.8V 1. 5 mS 500 mS Can be overridden by communication command. 4.3.4 Port Current Monitoring Table 11 * PD69208M Port Current Monitoring Parameter Conditions Typ Max Units Resolution Reported as 14 Bits 10 Bits LSB 122.07 A Measurement Period 16 mS Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 14 Electrical Specifications Table 11 * 4.3.5 PD69208M Port Current Monitoring (continued) Parameter Conditions Accuracy Typ Max Units 50 mA < IPORT < 150 mA 9 % 150 mA < IPORT < 350 mA 4.5 % 350 mA < IPORT < 600 mA 3.5 % IPORT > 600 mA 3.0 % Port Voltage Monitoring Table 12 * PD69208M Port Voltage Monitoring Parameter Typ Resolution 10 Bits LSB 58.6 mV Measurement Period 3 mS Accuracy 4.3.6 Max 3.3 Units % Main Voltage Monitoring Table 13 * PD69208M Main Voltage Monitoring Parameter Conditions Typ Max Units Resolution 10 Bits LSB 58.6 mV Measurement Period 3 mS Accuracy 42 V < VMAIN < 50 V 2 % 50 V < VMAIN < 57 V 1.5 % 0.6 % 50 V < VMAIN < 57 1. 4.3.7 V1 0-70 C Temperature Monitoring Table 14 * PD69208M Temperature Monitoring Parameter Conditions Min Resolution LSB Temperature = (DATA x 1.9384) - 273 Measurement Period Accuracy -3 Typ Max Units 8 Bits 1.9384 C 3 mS 3 C Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 15 Electrical Specifications 4.3.8 Digital Interface Table 15 * PD69208M Digital Interface Symbol Parameter Conditions Min VIH Input Logic High Voltage RESET_N, MOSI, MISO, SCK, CS_N, PGD[0..3], ADDR[0..3] 2.2 VIL Input Logic Low Voltage RESET_N, MOSI, MISO, SCK, CS_N, PGD[0..3], ADDR[0..3] Hyst Input Logic Hysteresis Voltage RESET_N, MOSI, MISO, SCK, CS_N, PGD[0..3], ADDR[0..3] 0.4 IIH Input Logic High Current RESET_N, MOSI, MISO, SCK, CS_N, PGD[0..3], ADDR[0..3] IIL Input Logic Low Current VOH VOL 4.3.9 Typ Max Units V 0.8 V 0.8 V -10 10 A RESET_N, MOSI, MISO, SCK, CS_N, PGD[0..3], ADDR[0..3] -10 10 A Output Logic High Voltage RESET_N, MOSI, MISO, SCK, CS_N, PGD[0..3], ADDR[0..3] IOH = -1mA 2.4 Output Logic Low Voltage RESET_N, MOSI, MISO, SCK, CS_N, PGD[0..3], ADDR[0..3] IOH = 1mA 0.6 V 0.4 V Immunity Table 16 * Symbol ESD Surge 1. 2. 3. PD69208M Immunity Parameter Conditions ESD rating HBM1 ESD rating CDM2 Lightning surge3 EN61000 4-5 Min -1 Typ Max Units 1 KV ESD HBM complies with JESD22 Class 2 standard. ESD CDM complies with JESD22 Class 1 standard. System level common mode 10/700 S according to IEC61000-4-5. Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 16 Electrical Specifications 4.4 PD69208M Absolute Maximum Ratings PoE performance is not guaranteed when exceeding the recommended rating. Exposure to any stress in the range between the recommended rating, as listed in the following table, and the absolute maximum rating should be limited to a short time. Exceeding these ratings may impact long-term operating reliability. Table 17 * Absolute Maximum Ratings Parameters Min Max Units Supply Input Voltage (VMAIN)1, 2 -0.3 72 V PORT_NEG[0.7] pins -0.3 VMAIN+0.5 V VAUX5 -0.3 6 V VAUX3P3, DVDD -0.3 4 V Digital pins: MISO, MOSI, SCK, CS_N, ADDR[3:0], PGD[3:0], RESET_N, TRIM -0.3 DVDD + 0.3 and < 4.0 V Junction Temperature 150 C Lead Soldering Temperature (40s, reflow) 260 C 150 C Storage Temperature 1. 2. -65 Power Sequence Requirement: Vmain > VAUX5 > VAUX3P3= TRIM, DVDD. PD69208M EPAD is connected by copper plane on PCB to AGND. AGND is ground for IC. Note: DRV_VAUX5 and IREF are output pins and should not apply voltage or current. DRV_VAUX5 can be left open when not used. Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 17 Pin Descriptions 5 Pin Descriptions The PD69200 device has 32 pins and PD69208M device has 56 pins, which are described in this section. 5.1 Pin Configuration and Pinout The following figures represent the top- and bottom-view of PD69200 and PD69208M devices. 5HVHUYHG [5(6(7 (;7$/26&B,1 ,&B6&/ ,&B6'$ ;7$/26&B287 ,&B$''5B0($6 $QDORJB,1 009 966 9'' 5HVHUYHG10,BE 6:'B',2 (3$'3LQ ;;;;; [/('B2( [/('B/$7&+ [/('B&6 === [,17B287 [,&B0(66$*(B5($'< PD69200 Pin Diagram Figure 4 * 8$57B7; <<<<< )$1B&21752/ 8$57B5; [',6$%/(B32576 6:'B&/. $QDORJB,1 (63,B6&. (63,B026, (63,B0,62 9''$ 966$ (63,B[&6 8$57B5; 7239,(: 8$57B7; [6<6B2. *** %277209,(: i4)1/ i4)1/ Note: The marking position of PD69200 may change subject to NXP practice. Note: For definitions about markings in the PD69200 pinout diagram, see the ordering information table (Table 30, page 41). Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 18 Pin Descriptions PGD2 N.C RESET_N DVDD 44 43 ADDR1 49 45 ADDR2 50 46 ADDR3 51 ADDR0 CS_N 52 PGD3 SCK 53 47 MOSI 54 48 PGD0 MISO 56 55 54 53 52 51 50 49 48 47 46 45 44 43 56 PD69208M Pin Diagram 55 Figure 5 * N.C 1 42 DGND 42 1 TST 2 41 PGD1 41 2 VPORT_NEG0 3 40 VPORT_NEG7 40 3 VPORT_NEG0 4 39 VPORT_NEG7 39 4 5 38 RESERVED 38 5 6 37 VPORT_NEG6 37 6 VPORT_NEG1 7 36 VPORT_NEG6 36 RESERVED 8 35 RESERVED 35 8 VPORT_NEG2 9 34 VPORT_NEG5 34 9 VPORT_NEG2 10 33 VPORT_NEG5 33 10 RESERVED 11 32 RESERVED 32 11 VPORT_NEG3 12 31 VPORT_NEG4 31 12 VPORT_NEG3 13 30 VPORT_NEG4 30 13 RESERVED 14 29 RESERVED 29 14 PD69208M F R e4 24 25 26 27 28 IREF TRIM RESERVED RESERVED AGND VAUX5 23 20 DRV_VAUX5 VAUX3P3_INT 19 22 18 N.C AGND 17 VMAIN VAUX3P3 16 21 15 15 16 17 18 19 21 20 22 23 24 25 26 AGND 7 EPAD 27 RESERVED DATE CODE 28 RESERVED VPORT_NEG1 Bottom View - 8x8 QFN - 56L Top View - 8x8 QFN - 56L Note: For definitions about markings in the PD69208M pinout diagram, see the ordering information table (Table 30, page 41). 5.2 Pin Descriptions The following sections describe the functional pin descriptions of PD69200 and PD69208M devices. 5.2.1 PD69200 The following table lists the functional pin descriptions of the PD69200 device. Table 18 * PD69200 Pin Description Number Designator Type Description EPAD Thermal Isolated Thermal PAD, recommended to tie to GND. 1 UART1_TX1 OUT Reserved UART. 2 UART1_RX1 IN Reserved UART. 3 ESPI_xCS OUT ESPI Bus to PoE Manager. SPI chip select (Active Low). CS is asserted during all SPI frame. 4 ESPI_SCK OUT ESPI Bus to PoE Manager. SPI clock output to PD6920x, and LED stream clock output, set to 1 MHz. 5 ESPI_MOSI OUT SPI packets are transmitted on this line. 6 ESPI_MISO IN ESPI Bus to PoE Manager. SPI Master In Slave Out. SPI packets are received on this line. 7 VDDA Supply Main Supply 3.3 V. 8 VSSA GND Analog ground. 9 Analog_IN Analog_IN Analog input. Should be connected to 3.3 V. 10 SWD_CLK DEBUG Serial Debug Data Bus Clock. Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 19 Pin Descriptions Table 18 * PD69200 Pin Description (continued) Number Designator Type Description 11 UART0_RX1 IN UART receive from host. 15 byte protocol commands are received on this line. The baud rate is set to 19,200 bps. For more information, see the Serial Communication Protocol User Guide document - Catalog Number: PD69200_UG_COMM_PROT. 12 UART0_TX1 OUT UART transmit to host. 15 byte protocol reply/telemetry are transmitted on this line. The baud rate is set to 19,200 bps. For more information, see the Serial Communication Protocol User Guide document - Catalog Number: PD69200_UG_COMM_PROT. 13 SWD_DIO DEBUG Serial Debug Data Bus. 14 Reserved (NMI_b) IRQ_Input Spare, an external pull-up must be connected. 15 VDD Supply Main Supply 3.3 V. 16 VSS GND Digital ground. 17 EXTAL0 (OSC_IN)2 Oscillator Oscillator input - Reserved. Oscillator Oscillator output - Reserved. IN/OUT Host Reset input (Active Low). The shortest reset pulse from the host that is required for the PD69200 application is 150 Sec. PD69200 can generate self-reset. In this case, the xRESET pin is driven low by the PD69200 for about 100 Sec. It is recommended to connect this pin to a host open drain output with 10 K pull-up. An 47 nF filter capacitor should be connected between this pin to GND, close to the PD69200 device. If this pin is connected to a push/pull driver, a serial resistor of 1.5 K must be connected instead of the pull-up. The required shortest reset pulse in this case is 300 Sec. (OSC_OUT)2 18 XTAL0 19 xRESET(3,4) For more information about this pin connectivity, see the Hardware Application Note, Catalog Number: PD69208_AN_211. 20 I2C0_SCL4 IN/OUT I2C clock from the host master. Speed is limited to 400 KHz and clock stretching functionality must be implemented in the host master. If PD69200 is busy, it holds the clock line. 21 I2C0_SDA4 IN/OUT I2C bidirectional data. 15 byte protocol messages are transmitted on this line. For more information, see the Serial Communication Protocol User Guide document - Catalog Number: PD69200_UG_COMM_PROT. 22 I2C_ADDR_MEAS Analog_IN I2C address of PD69200. Analog input to determine I2C address or UART operation. See I2C address selection in Table 5, page 10. 23 Analog_IN Analog_IN Reserved analog input. connect to GND. 24 xI2C_MESSAGE_READY3 OUT I2C message ready for read by the host. PD69200 asserts this line low when it has an answer to the host. Therefore, the host can poll this line and initiate I2C read cycle only when the message is ready. This pin is active low. After the host reads the data from PD69200, this pin is asserted to high. Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 20 Pin Descriptions Table 18 * PD69200 Pin Description (continued) Number Designator Type Description 25 xINT_OUT(3, 4) OUT Interrupt output indication. This line is asserted low when a pre-configured event is in progress. The host configures the event that should generate an interrupt through 15 bytes protocol. When this event occurs, the xINT_OUT pin is asserted. This pin is active low. 26 xLED_CS3 OUT Chip select signal for LED stream. This pin is active low. 27 xLED_LATCH3 OUT Latch signal for LED stream. This pin is active low. 3 28 xLED_OE OUT Output enable signal for LED stream. This pin is active low. 29 Reserved IN Reserved for MPRPD counter for future support. If not used, connect to VDD. 30 FAN_CONTROL OUT Optional. Fan control operates a fan, when the PD69208M device temperature is above the temperature alarm threshold. This pin is active high. 31 xDISABLE_PORTS3 IN Disable all PoE ports. When this input is asserted low, the PD69200 device shuts down all of the PoE ports in the system. This pin contains software filter of 480 mSec to reject noise and false disable scenarios. 32 xSys_OK/LED System OK3 OUT System validity indication. When the system is in OK state, the pin state is low. The behavior of this output is controlled by software mask register settings (Mask 0x28). The mask default settings is 0, meaning that this pin indicates valid software, and Vmain is in range. This pin is active low. For more information, see the Serial Communication Protocol User Guide document - Catalog Number: PD69200_UG_COMM_PROT. 1. 2. 3. 4. Weak pull-up is recommended. See the PD69208_AN_211 document. The oscillator pins are reserved and unused. The MCU uses internal clock source set to 47.972MHz +/- 1.5% (max). The initial x indicates that the pin is active low. Open drain output requires an external pull-up. See the Hardware Application Note: PD69208_AN_211 document. Note: All I/Os in this application can sink or source 3 mA maximum. 5.2.2 PD69208M The following table lists the functional pin descriptions of PD69208M devices Table 19 * Number PD69208M Pin Description Designator Type EPAD Description Exposed PAD. Connect to analog ground. A decent ground plane should be deployed around this pin as required. See the PD69208M Layout Design Guidelines section in the Hardware Application Note, Catalog Number: PD69208M_AN_211. 1 N.C N/A Not connected; do not connect externally (leave floating). 2 TST Digital Input Test pin for production use only. Keep connected to DGND. 3 VPORT_NEG0 Analog I/O Negative port 0 output. 4 VPORT_NEG0 Analog I/O Negative port 0 output. 5 RESERVED N/A Reserved pin. Do not connect externally. 6 VPORT_NEG1 Analog I/O Negative port1 output. Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 21 Pin Descriptions Table 19 * PD69208M Pin Description (continued) Number Designator Type Description 7 VPORT_NEG1 Analog I/O Negative port1 output. 8 RESERVED N/A Reserved pin. Do not connect externally. 9 VPORT_NEG2 Analog I/O Negative port 2 output. 10 VPORT_NEG2 Analog I/O Negative port 2 output. 11 RESERVED N/A Reserved pin. Do not connect externally. 12 VPORT_NEG3 Analog I/O Negative port 3 output. 13 VPORT_NEG3 Analog I/O Negative port 3 output. 14 RESERVED N/A Reserved pin. Do not connect externally. 15 AGND Power Analog ground. 16 RESERVED N/A Reserved pin. Do not connect externally. 17 VMAIN Power Main high-voltage supply voltage. A low ESR 1 F (or higher) bypass capacitor, connected to AGND, should be placed as close as possible to this pin through low-resistance traces. 18 N.C N/A Not connected. Do not connect externally. 19 DRV_VAUX5 Power Driven outputs for 5 V external regulation; if internal regulation is used, connect to pin 20. If an external NPN is used to regulate the voltage, connect this pin to Base. If an NPN is used, a 4.7 F capacitor should be connected between this pin and AGND. 20 VAUX5 Power Regulated 5 V output voltage source; A 4.7 F or higher filtering capacitor should be connected between this pin and AGND. If an external NPN is used to regulate the voltage, connect this pin to the emitter. Or the collector should be connected to Vmain. 21 AGND Power Analog ground. 22 VAUX3P3 Power Regulated 3.3 V output voltage source. A 4.7 F or higher filtering capacitor should be connected between this pin and AGND.When an external 3.3 V regulator is used, connect it to this pin to supply the chip. 23 VAUX3P3_INT Power Connected to VAUX3P3 (pin 22) if internal 3.3 V regulator is used. Leave unconnected (Floating) if external 3.3 V regulator is used. 24 IREF Analog Input Reference resistor pin. Connect a 28.7 k 1% resistor to AGND. 25 TRIM Test Input Test Input pin; Keep connected to VAUX3P3. 26 RESERVED N/A Reserved pin. Do not connect externally. 27 RESERVED N/A Reserved pin. Do not connect externally. 28 AGND Power Analog ground. 29 RESERVED N/A Reserved pin. Do not connect externally. 30 VPORT_NEG4 Analog I/O Negative port 4 output. 31 VPORT_NEG4 Analog I/O Negative port 4 output. 32 RESERVED N/A Reserved pin. Do not connect externally. 33 VPORT_NEG5 Analog I/O Negative port 5 output. 34 VPORT_NEG5 Analog I/O Negative port 5 output. 35 RESERVED N/A Reserved pin. Do not connect externally. Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 22 Pin Descriptions Table 19 * PD69208M Pin Description (continued) Number Designator Type Description 36 VPORT_NEG6 Analog I/O Negative port 6 output. 37 VPORT_NEG6 Analog I/O Negative port 6 output. 38 RESERVED N/A Reserved pin. Do not connect externally. 39 VPORT_NEG7 Analog I/O Negative port 7 output. 40 VPORT_NEG7 Analog I/O Negative port 7 output. 41 PGD1 Digital I/O Power good input from system power supply. 42 DGND Power Digital ground. 43 DVDD Power In Regulated 3.3 V for digital circuitry. Connect voltage from pin VAUX3P3 or from external power supply source if used. A 1 F or higher filtering capacitor should be connected between this pin and DGND. 44 RESET_N Digital Input Reset input - active low (0 = reset). An external 10 K pull-up resistor should be connected between this pin and DVDD. 45 N.C N/A Not connected. Do not connect externally. 46 PGD2 Digital Input Power good input from system power supply. 47 PGD3 Digital Input Power good input from system power supply. 48 ADDR0 Digital Input SPI address bit 0 to set chip address. 49 ADDR1 Digital Input SPI address bit 1 to set chip address. 50 ADDR2 Digital Input SPI address bit 2 to set chip address. 51 ADDR3 Digital Input SPI address bit 3 to set chip address. 52 CS_N Digital Input SPI bus and chip select. 53 SCK Digital Input SPI bus and serial clock input. 54 MOSI Digital Input SPI bus and Master Data Out/slave In. 55 MISO Digital Output SPI bus and Master Data In/slave Out. 56 PGD0 Digital Input Power good input from system power supply. Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 23 Pin Descriptions 5.3 PD69200 Recommended PCB Layout for 32 Pin QFN 5mm x 5mm The following figures illustrate the PCB layout pattern for PD69200. Units are in mm. Figure 6 * PD69200 Top-Layer Copper PCB Layout 6ROGHU3DVWH Figure 7 * PD69200 Top-Layer Solder Paste and Vias PCB Layout for Thermal Pad Array 6ROGHU3DVWH Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 24 Pin Descriptions 5.4 PD69208M Recommended PCB Layout for 56-Pin QFN 8mm x 8mm The following figures illustrate the PCB layout pattern for PD69208M. Units are in mm. Top-Copper Layer 8QLWVLQ0LOOLPHWHUPP Figure 8 * Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 25 Pin Descriptions Top-Solder Paste Layer 8QLWVLQ0LOOLPHWHUPP Figure 9 * Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 26 Pin Descriptions Figure 10 * Top-Layer Mask Figure 11 * BOT and Internal Layers Copper Plane 8QLWVLQ0LOOLPHWHUPP Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 27 Pin Descriptions Figure 12 * Top-Layer Pin Geometry 8QLWVLQ0LOOLPHWHUPP 3DVWH 0HWDO 0DVN Note: The CM has latitude to modify the solder paste stencil for manufacturability reasons. The solder paste stencil shall cover 65% to 80% of the thermal pad and must not allow solder to be applied to the thermal vias under the QFN package using any method they deem appropriate. Any design should be subject to system validation and qualification prior to commitment to mass production of field deployment. Use a 5 mil stencil. Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 28 Package Information 6 Package Information This chapter describes package drawings of PD69200 and PD69208Mdevices. 6.1 PD69200 Package Outline Drawing The following figure illustrates the package drawing of PD69200 device. Figure 13 * PD69200 Package Outline Drawing (32 Pin QFN 5 mm x 5 mm) ' . ' / ( ( H E $ $ $ The following table lists the dimensions and measurements of the PD69200 package. Table 20 * PD69200 Package Outline Dimensions and Measurements Dimension Millimeters Inches Min Max Min Max A 0.80 1.00 0.031 0.039 A1 0.00 0.05 0 0.002 A3 0.20 REF 0.008 REF K 0.20 MIN 0.008 MIN e 0.50 BSC 0.02 BSC L 0.30 0.50 0.012 0.02 b 0.18 0.30 0.007 0.012 D2 3.50 3.70 0.138 0.147 E2 3.50 3.70 0.138 0.147 D 5.00 BSC 0.197 BSC E 5.00 BSC 0.197 BSC Note: Dimensions do not include protrusions; they should not exceed 0.155 mm (.006) on any side. Lead dimension should not include solder coverage. Dimensions are in millimeters and inches for reference. Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 29 Package Information 6.2 PD69208M Package Outline Drawing The following figure illustrates the package drawing of the PD69208Mpackage. Figure 14 * PD69208M Package Drawing (56 Pin QFN 8 mm x 8 mm) ' / ' . ( ( H E $ $ $ The following table lists the dimensions and measurements of the PD69208Mpackage. Table 21 * PD69208MPackage Outline Dimensions and Measurements Dimension Millimeters Inches Min Max Min Max A 0.80 1.00 0.031 0.039 A1 0.00 0.05 0 0.002 A3 0.20 REF 0.008 REF K 0.20 MIN 0.008 MIN e 0.50 BSC 0.02 BSC L 0.30 0.50 0.012 0.02 b 0.18 0.30 0.007 0.012 D2 6.50 6.75 0.256 0.267 E2 6.50 6.75 0.256 0.267 D 8.00 BSC 0.315 BSC E 8.00 BSC 0.315 BSC Note: Dimensions do not include protrusions; they should not exceed 0.155mm (.006) on any side. Lead dimension should not include solder coverage. Dimensions are in millimeters and inches for reference. Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 30 Package Information 6.3 PD69208M Thermal Specifications The following tables list the thermal specifications of PD69208M and PD69200. Table 22 * PD69208M Thermal Specifications Thermal Resistance Typ Units Notes JA 19.0 C/W Junction-to-ambient thermal resistance. JT 0.05 C/W Junction-to-top thermal characterization parameter. A thermal metric derived from the difference in junction temperature (TJ) and package top temperature (TT) divided by total heating power (PH). JC (top) 4.9 C/W Junction-to-case thermal resistance with heat flow through package top. JB 2.2 C/W Junction-to-board thermal resistance. Note: All parameters are as per JEDEC JESD-51. Table 23 * 6.4 PD69200 Thermal Specifications Thermal Resistance Typ Units Notes JA 33 C/W Junction-to-ambient thermal resistance. JT 8 C/W Junction-to-top thermal characterization parameter. A thermal metric derived from the difference in junction temperature (TJ) and package top temperature (TT) divided by total heating power (PH). JC (top) 1.8 C/W Junction-to-case thermal resistance with heat flow through package top. JB 12 C/W Junction-to-board thermal resistance. Recommended Solder Reflow Information * * * RoHS 6/6 Pb-free 100% Matte Tin Finish Package Peak Temperature for Solder Reflow(40 seconds maximum exposure)--260 C (+0 C, -5 C) Table 24 * Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly Average Ramp-up Rate (TSmax to Tp) 3 C/second max 3 C/second max Preheat Temperature Min (TSmin) Temperature Max (TSmax) Time (tsmin to tsmax) 150 C 200 C 60 - 180 seconds 100 C 150 C 60 - 120 seconds Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 31 Package Information Table 24 * Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly Time Maintained Temperature (TL) Time (tL) 183 C 60 - 150 seconds 217 C 60 - 150 seconds Peak Classification Temperature (TP) 210 - 235 C 240 - 255 C Time within 5 C of actual peak temperature (tp) 10 - 30 seconds 20 - 40 seconds Ramp-Down Rate 6 C/second max 6 C/second max Time 25 C to Peak Temperature 6 minutes max 8 minutes max Figure 15 * Classification Reflow Profiles Table 25 * Pb-Free Process - Package Classification Reflow Temperatures Volume mm3 350 - 2000 Volume mm3 > 2000 260 +0 C 260 +0 C 260 +0 C 260 +0 C 250 +0 C 245 +0 C 250 +0 C 245 +0 C 245 +0 C Package Thickness Volume < 1.6 mm1 1.6 mm - 2.5 2.5 1. mm1 mm1 mm3 < 350 Tolerance: The device manufacturer or supplier should assure process compatibility up to and including the stated classification temperature, meaning that the Peak reflow temperature is +0 C. For example, 260 C to 0 C, at the rated MSL value. Note: Exceeding the ratings that are mentioned in Table 25, page 32 may cause damage to the device. Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 32 Package Information 6.5 Tape and Reel--Packaging Information The following sections provide the tape and reel information. 6.5.1 PD69200 Tape and Reel Specification Figure 16 * PD69200 Tape Specification The following table lists the PD69200 tape mechanical data. Table 26 * PD69200 Tape Mechanical Data Dimensions Value (mm) Value (inches) D 1.50 + 0.1/0 0.059 + 0.004/0 E 1.75 0.1 0.069 0.004 P0 4.00 0.1 0.157 0.004 T (max) 0.3 0.05 0.0118 0.003 D1 1.5 0.059 F 5.5 0.1 0.216 0.003 K (max) 1.6 0.1 0.0.63 0.004 P2 2.00 0.1 0.079 0.004 R 30 1.181 W 12.00 0.3 0.472 0.012 P1 8.00 0.1 0.31 0.004 K0 1.1 0.043 A0 5.30 0.208 B0 5.30 0.208 Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 33 Package Information Figure 17 * PD69200 Reel Specification The following table lists the PD69200 reel mechanical data. Table 27 * 6.5.2 PD69200 Reel Mechanical Data Dimensions Value (mm) Value (inches) Tape size 12 +0.3 0.472 +0.012 W1 12.4 0.488 W2 18.4 0.724 W3 15.4 0.606 PD69208M Tape and Reel Specification Figure 18 * PD69208M Tape and Reel Pin-1 Orientation Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 34 Package Information Figure 19 * PD69208M Tape Specifications The following table lists the PD69208M tape mechanical data. Table 28 * PD69208M Tape Mechanical Data Dimension Value (mm) A0 8.35 0.10 B0 8.35 0.10 K0 1.40 0.10 K1 N/A Pitch 12.00 0.10 Width 16.00 0.30 Figure 20 * PD69208M Reel Specifications Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 35 Package Information Table 29 * 6.6 PD69208M Reel Mechanical Data Dimensions Value (mm) Value (inch) Tape size 16.00 0.3 0.630 0.012 A max. 330 13" B max 1.5 0.059 C 13.0 0.20 0.512 0.008 D min. 20.2 0.795 N min. 50 1.968 G 16.4+2.0/-0.0 0.645+ 0.079/-0.0 T max 29 1.142 BASE QUANTITY 2000 pcs. Reference Documents * * * * * * * IEEE Std 802.3-2018 Clause 33 Power over Ethernet over 2-Pair and Clause 145 Power over Ethernet Microsemi, Serial communication protocol user guide, Catalog Number: PD69200_UG_COMM_PROT Microsemi, Designing 48-port Enhanced PoE System (802.3af/802.3at Compliant) application note, Catalog Number: PD69208_AN_211 Microsemi, Software Download Algorithm technical note (TN-140), Catalog Number: 06-0024-081 Microsemi, PoE LED stream technical note, Catalog Number: PD69100_TN_201 NXP, Kinetis_L MKL15Z128VFM4 datasheet NXP package drawings 98ASA00473D Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 36 Application Information 7 Application Information PD69208M/PD69200 PSE Chipset performs IEEE802.3af (Type 1), IEEE802.3at (Type 2), and IEEE802.3bt (Type 3) PSE functionalities in addition to pre-standard and legacy (capacitor) detection. Moreover, it includes additional protections such as short circuit and dV/dT protection upon startup. Note: IEEE802.3bt functionality will be enabled by a firmware upgrade. 7.1 PD Detection The PD detection feature detects a valid IEEE802.3af, IEEE802.3at or IEEE802.3bt. The PD detection is done based on four different voltage levels generated over PD (the load) as illustrated in Figure 22, page 38. 7.2 Legacy (Reduced Capacitor) Detection When legacy detection is enabled, the PD detection mechanism detects and powers up legacy and pre-standard PDs as well as IEEE802.3af, IEEE802.3at and IEEE802.3bt standard compliant PDs (Classes 0 - 6). 7.3 Classification The classification process takes place immediately after PD detection is successfully completed. The goal of the classification process is to detect PD class as specified in IEEE802.3 standards. In IEEE802.3af mode, the classification mechanism is based on a single voltage level (single event). In IEEE802.3at and IEEE802.3bt modes, the classification mechanism is based on two voltage levels (multiple events) as defined in IEEE802.3-2015 Clause 33 and IEEE802.3bt. Figure 21 * 4-Pair PoE System Diagram 36( 3' 90$,1 )9 ,&B6&/ ,&B6'$ ,& 3RZHU6XSSO\ 5- 5- 90$,1 933 8$57B7; 8$57B5; 8$57 '$7$ 3257B1(*[ Q)9 '$7$ 3'0 &RQWURO%ORFN 3' [5(6(7B,1 [',6$%/(B32576 [,17B287 [/('B&6 [/('B2( [/('B/$7&+ 026, 6&. 3257B1(*\ )9 5'(7 3'[[ 5&/$66 5&/6 N 55() 931B,1 '$7$ '$7$32:(5 (3$' % Q)9 '$7$ $*1' '*1' ,5() '$7$ '$7$32:(5 9$8; 7R3:0 9$8; 933 N '$7$ /('V 2873 )9 . $ 60$-$ !)9 60$-$ +267 '$7$ '$7$32:(5 9 '$7$ '$7$32:(5 9312 2871 ,QSXW *URXQG 3DLU$SSOLFDWLRQ2SWLRQDO&RQQHFWLRQ 6LQJOH ,GHDO%ULGJH3' . Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 37 Application Information Figure 22 * Typical IEEE802.3at Port PoE Voltage Diagram 3RZHU21 3RUW9ROWDJH (YHQWV&ODVVLILFDWLRQ 3KDVH 'HWHFWLRQ 3KDVH 7.4 )) HU2 3RZ 6WDUW8S ,QUXVK Port Start Up Upon a successful detection and classification process, power is applied to the load via a controlled start up mechanism. During this period, inrush current is limited to 425 mA for a typical duration of 65 mS, which allows PD load to charge and allows steady state of power condition. 7.5 Over-Load Detection and Port Shut Down After power up, PD69208M automatically initializes its internal protection mechanisms. These mechanisms are used to monitor and disconnect power from the PD when extreme conditions occur, as specified in the IEEE802.3 standards. These conditions include over-current or short ports terminals scenarios. 7.6 Disconnect Detection PD69208M supports the DC disconnect function as per IEEE802.3 standards. This mechanism continuously monitors load current and disconnects power according to IUDL, TMPDO, and TMPS parameters as specified in Table 10, page 14. 7.7 IC Thermal Monitoring PD69208M contain a thermal sensor that is sampled by the PD69200 for every 20 mS so that the PD69208M die temperature is monitored at all times. If the die exceeds the temperature limit (150 C), the system ports are disconnected to protect the PD69208M ICs. A temperature alarm threshold can be set by PD69200 controller to send interrupt indication by the xINT_OUT pin before ports are disconnected. The temperature can be read and monitored by the host as well, if required. 7.8 Over-Temperature Protection In addition to the die thermal sensor, there are thermal sensors on each MOSFET that continuously monitors each port main MOSFETs junction temperature, and shuts down the port load power when the temperature exceeds 200 C. 7.9 VMAIN Out of Range Protection The system automatically disconnects ports power when VMAIN exceeds the pre-configured over-voltage and under-voltage thresholds. Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 38 Application Information 7.10 2-Pair and 4-Pair Ports Operation modes include the following: * POE Type 1/2 class 0-4 (up to 30 W) * POE Type 3 class 0-4 2-Pair and class 5-6 4-Pair (up to 60 W) Note: For more information about 4-Pair operation modes and power configuration, see Microsemi_PoE_4_Pair_Behavior_PD6920x_PSE_Application_Note_160159. 7.11 Power Management System supports three power management modes: * * * 7.12 Class (LLDP and CDP) Dynamic Static Port Power Limit Port power limit (PPL) is used to configure port power limit. When a port exceeds the power limit, it gets disconnected automatically. 7.13 Reset Pin xRESET pin is PD69200 digital host reset input (Active Low). The shortest pulse that is guaranteed to be recognized is 100 nSec. PD69200 can generate self-reset. The xRESET pin is driven low by PD69200 for at least 128 bus clock cycles until the flash initialization has completed. It is recommended to connect this pin to a host open drain output with pull-up in a range of 4.7 K to 10 K. If this pin is connected to a push/pull driver, a serial resistor of 4.7 K must be connected instead of pull-up. Avoid resetting the PD69208M IC directly by the RESET_N pin. The PD69200 controls the PD69208M ICs if system reset is needed. For more information about this pin connectivity, see the hardware application note, Catalog Number: PD69208_AN_211. 7.14 System OK Indication Digital output pin to host is used as a system validity indication. When system is OK pin state is low. The behavior of this output is controlled by software mask register settings (Mask 0x28). The mask default settings is 0, meaning that this pin indicates valid software and Vmain is in range. This pin is active low. For more information, see the Serial Communication Protocol User Guide document - Catalog Number: PD69200_UG_COMM_PROT. 7.15 Interrupt Pin Interrupt out from PoE controller, indicating events such as: port on, port off, port fault, PoE device fault, voltage out of range, and more. For a full list of interrupt events, see the Serial Communication Protocol User Guide document - Catalog Number: PD69200_UG_COMM_PROT. This pin is active low. 7.16 Port Matrix Control Port matrix control enables layout designers to ascribe each physical port in the system to a logical port if required. 7.17 Power Good Interrupt Interrupt from power supply directly to PD69208M manager. For systems comprising more than a single power supply, in case one power supply fails, a port shutdown mechanism is executed to maintain operation and prevent collapse of other power supplies. When function is used, PGD0, PGD1, PGD2, and PGD3 should be connected to main power supplies status indication pin. Any change of at least 1 S on these lines triggers a pre-defined disconnection Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 39 Application Information matrix. This matrix is defined by PD69200 system power parameters. The port shutdown function reacts within 2 S to any power good event. 7.18 LED Stream The direct SPI interface to an external LED stream circuitry that can drive LEDs directly without the host intervention. It enables designers to implement a simple LED circuit that does not require a software code. The LED stream clock frequency is 1 MHz. For more information, see the TN-218, catalog number PD69200_TN_218. 7.19 Power Sequencing Figure 23 * Power Sequencing 9 9PDLQ 9 9 7G 7G 7G 7 7G When using external Vaux5 or Vaux3p3 * Td1: Vmain at 5 V to Vaux5 > 0 S * Td2: Vaux5 to Vaux3p3 > 0 S * Td3: Vaux3p3 to Vaux5 > 0 S * Td4: Vaux5 to Vmain at 5 V > 0 S * DVDD = Vaux3p3 Note: See the Application Note AN211 - Designing a PD69208 48-port PoE System 802.3af/802.3at compliant. For proper operations, you need to ensure that Vmain is always in the highest voltage connected to the IC. With an external DC-DC converter, the maximum 3.3 V slew rate is 100 mS. Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 40 Ordering Information 8 Ordering Information The following table the part ordering information for PD69200 and PD69208M devices. Table 30 * Ordering Information Part Number Package Packaging Type Temperature Part Marking Tray Marking Plastic QFN Tray 5 mm x 5 mm (32 lead) -40 C to 85 C Microsemi Logo NXP Logo 69200 M15M7V4 XXXXX5 YYYYY6 PD69200DVVVVSS PD-OOOOG3bb7 YYWW PD69200D-VVVVSS-TR Plastic QFN Tape and 5 mm x 5 mm Reel (32 lead) -40 C to 85 C Microsemi Logo NXP Logo 69200 M15M7V4 XXXXX5 YYYYY6 PD69200VVVVSS-TR PD-OOOOT3bb7 YYWW PD69208MILQ-TR-LE Plastic QFN Tape and 8 mm x 8 mm Reel (56 lead) -40 C to 85 C Microsemi Logo PD69208M F R e48 YYWWAZZ9 PD69208MILQ-TR Plastic QFN Tape and 8 mm x 8 mm Reel (56 lead) -40 C to 85 C Microsemi Logo PD69208M F R e48 YYWWAZZ9 PD69200D1 2 3 -VVVV SS 1. 2. 3. 4. 5. 6. 7. 8. 9. D stands for the detection method set as: C: Detection Method = IEEE802.3 and pre-standard; R: Detection Method = IEEE802.3. VVVV is firmware revision SS stands for firmware parameters option Short part number Mask set Date code MKTG Product Type (Detection = R: Resistor/D = C: Resistor/Legacy)/Version/SW Parameters/Operation P/N. F = FAB Code, R = Product revision code (D for V2R2 and E for V2R4), and e4 = 2nd level interconnect. YY = Year, WW = Week, A = Assembly location, and ZZ = assembly lot sequence code. The Firmware Release Notes has all the required information about how to specify the choice of VVVV and SS. You can find the Firmware Release Notes in the Microchip Software Libraries, and register yourself to a My Microchip account to have access to the release notes. Note: The package meets RoHS, Pb-free, and MSL3 of the European Council to minimize the environmental impact of electrical equipment. Note: Initial burning of controller's firmware is performed in factory. Firmware upgrades can be performed by users using communication interface. For more information, see TN-140, Catalog Number: 06-0024-081. Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 41 Ordering Information The following table lists the manufacturing and ordering part numbers of PD69208M devices. Table 31 * PD69208M Manufacturing and Ordering Part Numbers Ordering Part Number Die Revision Product Revision Code Manufacturing Part Number PD69208MILQ-TR-LE V2R4 E PD69208MILQ-TR-LE PD69208MILQ-TR V2R4 E PD69208MILQ-TR-LE Customers can order the PD69208M device using either the ordering part number or the manufacturing part number. See Table 30, page 41 for package, packing type, temperature, and part marking information. Microsemi Proprietary and Confidential PD69208M and PD69200 Datasheet Revision 5.0 42