Monolithic fe Memortles 16x16 Bit CMOS Multiplier 67C7016 - 35/- 45/-55 6707017 -35/-45/-55 SIISIAITITTTI IIMA DVANCE INFORMATION Features/ Benefits 16x16 parallet multiplier High speed multiply 35 ns Max '7016-35/'7017-35 45 ns Max '7016-45/'7017-45 55 ns Max '7016-55/'7017-55 Low power CMOS technology ~~ Zero standby power 7 mA per MHz active loc (Typical) e Mixed mode 2s complement, unsigned or mixed operand 7017 is optimized for microprocessor systems, single clock with register enables Plug-in compatible with TRW MPY016H/K, AMD29516/A, 29517/A Single 5 V supply Available in DIP or PLCC Functional Block Diagrams 6 670701 Y45-Yo/P15Po XigX Xm Yu b> REGISTER L REGISTER r- REGISTER CLKX 4 cLKY MULTIPLIER ARRAY OY FA - ___-| FORMAT ADJUST MSP LSP FT- | REGISTER | REGISTER b. cCLKM -~ ______] CLKL MSPSEL- MULTIPLEXER oer - Pay-Pig/P45-Pq This document contains information on a product under development at Monolithic Memories Inc. The information is intended to help you to evaluate this product. Packaging Information PART SPEED NUMBER (Tuc) PACKAGE TEMP 67C7016-35 35 ns J,N,NL(68) Com 67C07017-35 35 ns JN,NL(68) Com 67C7016-45 45 ns J,N,NL(68) com 67C07017-45 45 ns JN,NL(68) com 67C7016-55 55 ns JN,NL(68) Com 67C7017-55 55 ns JN,NL(68) Com 67C701 ? Y15-Yo/P15-Po XisXo Xm RND Yeu REGISTER Pm REGISTER r) L REGISTER CLK | ENX ENY MULTIPLIER ARRAY me FA FORMAT ADJUST Msp LSP FT >] REGISTER | REGISTER WA. ity ENP I MSPSEL MULTIPLEXER OEP Monolithic Memories reserves the right to change or discontinue work on this proposed product without notice. TWX: 910-338-2376 2175 Mission College Bivd. Santa Clara, CA 95054-1592 Tel: (408) 970-9700 TWX: 910-338-2374 P3y-Pr6/Pas-Po Monolithic Memorles 17-2367C7016-35/-45/-55 67C7017-35/-45/-55 Pin Configurations 67C7016 64 Pin DIP 67C7016 68 Pin PLCC P12 Y12 3] P10 10 3] P13 Y13 3] P14 Y14 SJ Ps 15 Fd & & 3} 4] my ia ie a j= 17-24 Monolithic ER Memorles67C7016 - 35/- 45/-55 6707017 - 35/- 45/- 55 Pin Configurations 6707017 64 Pin DIP 6707017 68 Pin DIP co ran oe wo wo he wo wo SEH FP EF om MR RR RR RR RR Re Re 28&aER & & WF ek TE RDA @ad E]BE] Bey 1351 Bel 3h B21 Tait Bol Peat Fea 27! ENY n/c cuk fis 2] P16 Po OEL [4 P17 P1 xofa 23] P18 P2 x16 P19 P3 x2h 21) P20 Pa xs fia P21 PS xe fig] P22 P6 xs Bi (ej P23 P7 xe Ei fi7] P24 PS x7 Ei fig] P25 PS xe [Bi P26 P10 xo fi 14] P27 P11 x1of p28 P12 x11 fi figy P29 P13 x12 [et ii] P30 P14 nvc fio ig] P31 1s Gigs 85) pes} 087) Wee) LL 27 2 15) 18 13] + + & Monolithic RD Memories 17-256707016 - 35/-45/-55 Descriptions The7016/7017 are CMOS 16x16 high speed parallel multipliers. Designed with state-of-the-art CMOS technology and a multi- plication scheme based on modified Booths algorithm, these devices can achieve bipolar TTL speed at a significantly reduced power level. in addition, the product is designed to be pin-for-pin replacement for the TRW MPY016H/K and the AMD 29516/A, 29517/A. The architecture of the 7016/7017 family generates a 32-bit product of two 16-bit input operands. Two 16-bit registers are provided for the X and Y operands. These operands can be spetified a8 either 2's complerhemt Ot artsignitel nuMhters through the XM and the YM control inputs. These two signals are regis- tered simultaneously at their respective operand clocks. At the output of the multiplier array a format adjust control (FA) allows the user to select either a full 32-bit product or a left shifted 31-bit product. Two 16-bit output registers are provided to hold the most and least significant halves of the result (MSP and LSP) as defined by FA. For asynchronous output these registers may be made transparent by taking the feed through control (FT) high. A round control (RND) allows the rounding of the MSP. This control is registered, and is entered at the rising edge of the logical OR of both CLKX and CLKY for the 7016 and is enabled by a LOW signal in either ENX or ENY in the 7017. the two halves of the product may be routed to a 16-bit three-state output port (P) via a multiplexer. In addition the LSP is con- nected to the Y-input port through a separate three-state buffer so that a 32-bit product can be available simultaneously. In the '7016, the X, Y, MSP and LSP registers have independent clocks (CLKX, CCLKY, CLKM, CLKL). The output multiplexer contro! (MSPSEL) uses a pin which is a supply ground in the TRW MPY16H. When this control is LOW the function is that of the MPY16H, thus allowing full compatibility. The '7017 differs in that it has a single clock input (CLK) and three register enables (ENX, ENY, ENP) for the two input regis- ters and the entire product. This facilitates the use of the part in microprocessor systems. In both parts data is entered into the registers on the positive edge of the clock. The 7016/7017 family has a wide variety of applications in high performance computers and cigital signal processing. In com- puter applications this multiplier can be used to construct numerical processing functional units (e.g., array processors, matrix processors, floating point multiplier/dividers etc.}. In digital signal processing the multiplier can be used to construct special algorithm engines for applications like digital filtering, FFT, speech recognition and synthesis, adaptive controls and image processing. Signal Description Input/Output data 6707017 - 35/-45/- 55 P31-P16: The most significant product (MSP) outputs. Input Clocks (67C7016 only) CLKX: The rising edge of this clock joads the input data (X15-XO) and the associated mode control signal XM into the input register. CLKY: The rising edge of this clock loads the input data (Y15-Y0) and the associated mode control signal YM into the input register. The rising edge of this clock loads the most signifi- cant product (MSP) output register. CHEE: | THe Feit dite ob ete Groth (vane ING (owt exfmitt- cant produet (LSP) output register. Input Clocks (67C7017 only) CLKM: CLK: The rising edge of this clock loads all input/output registers. ENX: Clock enable far the X15-X0 input register, XM imput register amd the round register. ENY: Clock emabie for tee 15-0 input register, YM imput register and the round register. ENP: Clock enable for the most significant product (MSP) and least significant product (LSP) register. Control Signals XM, YM: Mode control signals for the input data word. A low input indicates unsigned data format and a high input represents 2s complement data format. FA: Format Adjust. When this input is high, a full 32-bit product is produced in MSP and LSP registers. When this input is low, the sign bit will appear in the most significant bit of both the MSP and the LSP. In such cases only a31-bit product is provided. The FA input is required to be a high when either integer unsigned magnitude or mixed mode formats are used. (See the DATA FORMATS section for further detail.) FT: Flow-through. When this input is high, both the MSP __ register and the LSP register are transparent. OEL: Three-state enable signal for routing LSP to the __ Y/LSP I/O ports. OEP: Three-state enable signal for the product output port. RND: Round contro! signal for the most significant product (MSP). When this input is high, a one will be added to the most significant bit of the least significant pro- duct (LSP). This rounding operation is done before the output is sent to the format adjust clock. As a result, the tocation of this round bit in the final pro- duct depends on the FA input. When FA = 0, the round bit is added to location P14; when FA = 1, the round bit is added to iocation P15. The RND input is registered at the rising edge of the logical OR of both the CLKX and CLKY. In the single clock architecture, the RND register is enabled when either the X regis- ter or the Y register is enabled. MSPSEL: When the MSPSEL input is low, the MSP is available X15-X0: 16 bit data inputs. Y15-Y0: 16 bit data inputs. These inputs are multiplexed with for the output port. When this input is high, the LSPis the least significant product (LSP) outputs. available at the output port. P15-P0: The least significant product (LSP) outputs. These signals are multiplexed with the Y data inputs. The product term is available when OEL is low. Alterna- tively, these outputs can be accessed from the MSP output port when MSPSEL is high. 17-26 Monolithic Rd Memories