http://onsemi.com This document, MC74HC4051/D has been canceled and replaced by MC74HC4051A/D LAN was sent 9/28/01 MC54/74HC4051 MC74HC4052 MC54/74HC4053 Analog Multiplexers/ Demultiplexers MC54/74HC4051 MC74HC4052 MC54/74HC4053 High-Performance Silicon-Gate CMOS The MC54/74HC4051, MC74HC4052 and MC54/74HC4053 utilize silicon-gate CMOS technology to achieve fast propagation delays, low ON resistances, and low OFF leakage currents. These analog multiplexers/ demultiplexers control analog voltages that may vary across the complete power supply range (from VCC to VEE). The HC4051, HC4052 and HC4053 are identical in pinout to the metal-gate MC14051B, MC14052B and MC14053B. The Channel-Select inputs determine which one of the Analog Inputs/Outputs is to be connected, by means of an analog switch, to the Common Output/Input. When the Enable pin is HIGH, all analog switches are turned off. The Channel-Select and Enable inputs are compatible with standard CMOS outputs; with pullup resistors they are compatible with LSTTL outputs. These devices have been designed so that the ON resistance (Ron) is more linear over input voltage than R on of metal-gate CMOS analog switches. For multiplexers/demultiplexers with channel-select latches, see HC4351, HC4352 and HC4353. * Fast Switching and Propagation Speeds * Low Crosstalk Between Switches * Diode Protection on All Inputs/Outputs * Analog Power Supply Range (VCC - VEE) = 2.0 to 12.0 V * Digital (Control) Power Supply Range (VCC - GND) = 2.0 to 6.0 V * Improved Linearity and Lower ON Resistance Than Metal-Gate Counterparts * Low Noise * In Compliance With the Requirements of JEDEC Standard No. 7A * Chip Complexity: HC4051 -- 184 FETs or 46 Equivalent Gates HC4052 -- 168 FETs or 42 Equivalent Gates HC4053 -- 156 FETs or 39 Equivalent Gates 16 1 1 1 1 DW SUFFIX SOIC PACKAGE CASE 751G-02 1 DT SUFFIX TSSOP PACKAGE CASE 948F-01 16 16 ORDERING INFORMATION MC54HCXXXXJ MC74HCXXXXN MC74HCXXXXD MC74HCXXXXDW MC74HCXXXXDT Ceramic Plastic SOIC SOIC Wide TSSOP FUNCTION TABLE - MC54/74HC4051 Control Inputs Enable C L L L L L L L L H L L L L H H H H X COMMON OUTPUT/ INPUT X D SUFFIX SOIC PACKAGE CASE 751B-05 16 13 3 N SUFFIX PLASTIC PACKAGE CASE 648-08 16 LOGIC DIAGRAM MC54/74HC4051 Single-Pole, 8-Position Plus Common Off X0 14 X1 15 X2 ANALOG 12 MULTIPLEXER/ INPUTS/ X3 DEMULTIPLEXER OUTPUTS X4 1 5 X5 2 X6 4 X7 11 A CHANNEL 10 B SELECT 9 INPUTS C 6 ENABLE PIN 16 = VCC PIN 7 = VEE PIN 8 = GND J SUFFIX CERAMIC PACKAGE CASE 620-10 VCC X2 X1 X0 X3 A B C 16 15 14 13 12 11 10 9 6 7 1 2 3 4 5 X6 X X7 X5 Enable VEE L L H H L L H H X L H L H L H L H X ON Channels X0 X1 X2 X3 X4 X5 X6 X7 NONE X = Don't Care Pinout: MC54/74HC4051 (Top View) X4 Select B A 8 GND MC54/74HC4051 MC74HC4052 MC54/74HC4053 FUNCTION TABLE - MC74HC4052 LOGIC DIAGRAM MC74HC4052 Double-Pole, 4-Position Plus Common Off 12 ANALOG INPUTS/OUTPUTS CHANNELSELECT INPUTS X0 14 X1 15 X2 11 X3 Y0 Y1 Y2 Y3 A B ENABLE X SWITCH 13 COMMON OUTPUTS/INPUTS 2 Y SWITCH 3 Select Enable B A ON Channels L L L L H L L H H X L H L H X Y0 Y1 Y2 Y3 X 1 5 Control Inputs X0 X1 X2 X3 NONE X = Don't Care Y 4 Pinout: MC74HC4052 (Top View) 10 9 PIN 16 = VCC PIN 7 = VEE PIN 8 = GND 6 VCC X2 X1 X X0 X3 A B 16 15 14 13 12 11 10 9 6 7 1 2 3 4 5 Y0 Y2 Y Y3 Y1 Enable VEE 8 GND FUNCTION TABLE - MC54/74HC4053 LOGIC DIAGRAM MC54/74HC4053 Triple Single-Pole, Double-Position Plus Common Off 12 X0 13 X1 X SWITCH 2 ANALOG INPUTS/OUTPUTS Y0 1 Y1 Y SWITCH 5 Z0 3 Z1 Z SWITCH 14 15 4 Control Inputs Enable C L L L L L L L L H L L L L H H H H X X Y COMMON OUTPUTS/INPUTS Z Select B A L L H H L L H H X ON Channels L H L H L H L H X Z0 Z0 Z0 Z0 Z1 Z1 Z1 Z1 Y0 Y0 Y1 Y1 Y0 Y0 Y1 Y1 NONE X0 X1 X0 X1 X0 X1 X0 X1 X = Don't Care 11 A 10 B 9 C 6 ENABLE CHANNELSELECT INPUTS PIN 16 = VCC PIN 7 = VEE PIN 8 = GND Pinout: MC54/74HC4053 (Top View) VCC Y X X1 X0 A B C 16 15 14 13 12 11 10 9 6 7 NOTE: This device allows independent control of each switch. Channel-Select Input A controls the X-Switch, Input B controls the Y-Switch and Input C controls the Z-Switch 1 2 3 4 5 Y1 Y0 Z1 Z Z0 Enable VEE 8 GND MC54/74HC4051 MC74HC4052 MC54/74HC4053 IIIIIIIIIIIIIIIIIIIIIII III IIIIIIIIIIIIII IIIIII III IIIIIIIIIIIIIIIIIIIIIII III IIIIIIIIIIIIII IIIIII III III IIIIIIIIIIIIII IIIIII III III IIIIIIIIIIIIII IIIIII III III IIIIIIIIIIIIII IIIIII III III IIIIIIIIIIIIII IIIIII III III IIIIIIIIIIIIII IIIIII III III IIIIIIIIIIIIII IIIIII III III IIIIIIIIIIIIII IIIIII III III IIIIIIIIIIIIII IIIIII III III IIIIIIIIIIIIII IIIIII III III IIIIIIIIIIIIII IIIIII III III IIIIIIIIIIIIII IIIIII III III IIIIIIIIIIIIII IIIIII III MAXIMUM RATINGS* Symbol Parameter (Referenced to GND) (Referenced to VEE) Value Unit - 0.5 to + 7.0 - 0.5 to + 14.0 V VCC Positive DC Supply Voltage VEE Negative DC Supply Voltage (Referenced to GND) - 7.0 to + 5.0 V VIS Analog Input Voltage VEE - 0.5 to VCC + 0.5 V Vin Digital Input Voltage (Referenced to GND) - 0.5 to VCC + 0.5 V DC Current, Into or Out of Any Pin 25 mA PD Power Dissipation in Still Air, Plastic or Ceramic DIP SOIC Package TSSOP Package 750 500 450 mW Tstg Storage Temperature Range - 65 to + 150 C TL Lead Temperature, 1 mm from Case for 10 Seconds Plastic DIP, SOIC or TSSOP Package Ceramic DIP I C 260 300 * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating -- Plastic DIP: - 10 mW/C from 65 to 125C Ceramic DIP: - 10 mW/C from 100 to 125C SOIC Package: - 7 mW/C from 65 to 125C TSSOP Package: - 6.1 mW/C from 65 to 125C IIII IIIIIIIIIIIIII III III III IIII IIIIIIIIIIIIII III III III IIII IIIIIIIIIIIIII III III III IIII IIIIIIIIIIIIII III III III IIII IIIIIIIIIIIIII III III III IIII IIIIIIIIIIIIII III III III IIII IIIIIIIIIIIIII III III III IIII IIIIIIIIIIIIII III III III IIII IIIIIIIIIIIIII III III III IIII IIIIIIIIIIIIII III III III IIII IIIIIIIIIIIIII III III III IIII IIIIIIIIIIIIII III III III RECOMMENDED OPERATING CONDITIONS Symbol Parameter (Referenced to GND) (Referenced to VEE) Min Max Unit 2.0 2.0 6.0 12.0 V VCC Positive DC Supply Voltage VEE Negative DC Supply Voltage, Output (Referenced to GND) - 6.0 GND V VIS Analog Input Voltage VEE VCC V Vin Digital Input Voltage (Referenced to GND) GND VCC V VIO* Static or Dynamic Voltage Across Switch 1.2 V - 55 + 125 C 0 0 0 1000 500 400 ns TA Operating Temperature Range, All Package Types tr, tf Input Rise/Fall Time (Channel Select or Enable Inputs) VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V * For voltage drops across switch greater than 1.2V (switch on), excessive VCC current may be drawn; i.e., the current out of the switch may contain both VCC and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded. This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. MC54/74HC4051 MC74HC4052 MC54/74HC4053 DC CHARACTERISTICS -- Digital Section (Voltages Referenced to GND) VEE = GND, Except Where Noted Condition Guaranteed Limit VCC V -55 to 25C 85C 125C Unit Symbol Parameter VIH Minimum High-Level Input Voltage, Channel-Select or Enable Inputs Ron = Per Spec 2.0 4.5 6.0 1.50 3.15 4.20 1.50 3.15 4.20 1.50 3.15 4.20 V VIL Maximum Low-Level Input Voltage, Channel-Select or Enable Inputs Ron = Per Spec 2.0 4.5 6.0 0.3 0.9 1.2 0.3 0.9 1.2 0.3 0.9 1.2 V Iin Maximum Input Leakage Current, Channel-Select or Enable Inputs Vin = VCC or GND, VEE = - 6.0 V 6.0 0.1 1.0 1.0 A ICC Maximum Quiescent Supply Current (per Package) Channel Select, Enable and VIS = VCC or GND; VEE = GND VEE = - 6.0 VIO = 0 V 6.0 6.0 2 8 20 80 40 160 A DC CHARACTERISTICS -- Analog Section Guaranteed Limit Symbol Ron Parameter Maximum "ON" Resistance VCC VEE -55 to 25C 85C 125C Unit Vin = VIL or VIH; VIS = VCC to VEE; IS 2.0 mA (Figures 1, 2) 4.5 4.5 6.0 0.0 - 4.5 - 6.0 190 120 100 240 150 125 280 170 140 Vin = VIL or VIH; VIS = VCC or VEE (Endpoints); IS 2.0 mA (Figures 1, 2) 4.5 4.5 6.0 0.0 - 4.5 - 6.0 150 100 80 190 125 100 230 140 115 Condition Ron Maximum Difference in "ON" Resistance Between Any Two Channels in the Same Package Vin = VIL or VIH; VIS = 1/2 (VCC - VEE); IS 2.0 mA 4.5 4.5 6.0 0.0 - 4.5 - 6.0 30 12 10 35 15 12 40 18 14 Ioff Maximum Off-Channel Leakage Current, Any One Channel Vin = VIL or VIH; VIO = VCC - VEE; Switch Off (Figure 3) 6.0 - 6.0 0.1 0.5 1.0 Maximum Off-Channel HC4051 Leakage Current, HC4052 Common Channel HC4053 Vin = VIL or VIH; VIO = VCC - VEE; Switch Off (Figure 4) 6.0 6.0 6.0 - 6.0 - 6.0 - 6.0 0.2 0.1 0.1 2.0 1.0 1.0 4.0 2.0 2.0 Maximum On-Channel HC4051 Leakage Current, HC4052 Channel-to-Channel HC4053 Vin = VIL or VIH; Switch-to-Switch = VCC - VEE; (Figure 5) 6.0 6.0 6.0 - 6.0 - 6.0 - 6.0 0.2 0.1 0.1 2.0 1.0 1.0 4.0 2.0 2.0 Ion A A MC54/74HC4051 MC74HC4052 MC54/74HC4053 AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns) Symbol Parameter Guaranteed Limit VCC V -55 to 25C 85C 125C Unit tPLH, tPHL Maximum Propagation Delay, Channel-Select to Analog Output (Figure 9) 2.0 4.5 6.0 370 74 63 465 93 79 550 110 94 ns tPLH, tPHL Maximum Propagation Delay, Analog Input to Analog Output (Figure 10) 2.0 4.5 6.0 60 12 10 75 15 13 90 18 15 ns tPLZ, tPHZ Maximum Propagation Delay, Enable to Analog Output (Figure 11) 2.0 4.5 6.0 290 58 49 364 73 62 430 86 73 ns tPZL, tPZH Maximum Propagation Delay, Enable to Analog Output (Figure 11) 2.0 4.5 6.0 345 69 59 435 87 74 515 103 87 ns Cin Maximum Input Capacitance, Channel-Select or Enable Inputs 10 10 10 pF CI/O Maximum Capacitance Analog I/O 35 35 35 pF Common O/I: HC4051 HC4052 HC4053 130 80 50 130 80 50 130 80 50 Feedthrough 1.0 1.0 1.0 (All Switches Off) Typical @ 25C, VCC = 5.0 V, VEE = 0 V CPD Power Dissipation Capacitance (Figure 13)* HC4051 HC4052 HC4053 45 80 45 pF MC54/74HC4051 MC74HC4052 MC54/74HC4053 ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0 V) Symbol BW -- -- -- THD Parameter Condition Maximum On-Channel Bandwidth or Minimum Mi i Frequency F Response R (Figure 6) fin = 1MHz Sine Wave; Adjust fin Voltage to Obt i 0dB Obtain 0dBm att VOS; IIncrease fin F Frequency Until dB Meter Reads -3dB; RL = 50, CL = 10pF Off-Channel Feedthrough Isolation (Figure 7) Feedthrough Noise. Channel-Select Input to Common I/O (Figure 8) Crosstalk Between Any Two Switches (Figure 12) (Test does not apply to HC4051) Total Harmonic Distortion (Figure 14) VCC V Limit* VEE V 25C `51 `52 `53 80 80 80 95 95 95 120 120 120 2.25 4.50 6.00 -2.25 -4.50 -6.00 fin = Sine Wave; Adjust fin Voltage to Obtain 0dBm at VIS fin = 10kHz, RL = 600, CL = 50pF 2.25 4.50 6.00 -2.25 -4.50 -6.00 -50 -50 -50 fin = 1.0MHz, RL = 50, CL = 10pF 2.25 4.50 6.00 -2.25 -4.50 -6.00 -40 -40 -40 Vin 1MHz Square Wave (tr = tf = 6ns); Adjust RL at Setup so that IS = 0A; Enable = GND RL = 600, CL = 50pF 2.25 4.50 6.00 -2.25 -4.50 -6.00 25 105 135 RL = 10k, CL = 10pF 2.25 4.50 6.00 -2.25 -4.50 -6.00 35 145 190 fin = Sine Wave; Adjust fin Voltage to Obtain 0dBm at VIS fin = 10kHz, RL = 600, CL = 50pF 2.25 4.50 6.00 -2.25 -4.50 -6.00 -50 -50 -50 fin = 1.0MHz, RL = 50, CL = 10pF 2.25 4.50 6.00 -2.25 -4.50 -6.00 -60 -60 -60 fin = 1kHz, RL = 10k, CL = 50pF THD = THDmeasured - THDsource VIS = 4.0VPP sine wave VIS = 8.0VPP sine wave VIS = 11.0VPP sine wave * Limits not tested. Determined by design and verified by qualification. Unit MHz dB mVPP dB % 2.25 4.50 6.00 -2.25 -4.50 -6.00 0.10 0.08 0.05 300 120 250 100 200 Ron , ON RESISTANCE (OHMS) Ron , ON RESISTANCE (OHMS) MC54/74HC4051 MC74HC4052 MC54/74HC4053 125C 150 25C 100 -55C 50 0 0 0.25 0.50 0.75 1.0 1.25 1.5 1.75 2.0 80 25C 60 -55C 40 20 0 2.25 125C 0 VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE 1.5 2.5 3.0 3.5 4.0 90 125C 75 25C Ron , ON RESISTANCE (OHMS) 105 60 45 -55C 30 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 75 Figure 1c. Typical On Resistance, VCC - VEE = 6.0 V 125C 60 25C 45 -55C 30 15 0 VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 Figure 1d. Typical On Resistance, VCC - VEE = 9.0 V PLOTTER 70 60 125C 50 25C 40 PROGRAMMABLE POWER SUPPLY - MINI COMPUTER VCC DEVICE UNDER TEST 20 ANALOG IN 10 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE Figure 1e. Typical On Resistance, VCC - VEE = 12.0 V DC ANALYZER + -55C 30 9.0 VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE 80 0 4.5 90 15 Ron , ON RESISTANCE (OHMS) 2.0 Figure 1b. Typical On Resistance, VCC - VEE = 4.5 V 120 Ron , ON RESISTANCE (OHMS) 1.0 VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE Figure 1a. Typical On Resistance, VCC - VEE = 2.0 V 0 0.5 GND COMMON OUT VEE Figure 2. On Resistance Test Set-Up MC54/74HC4051 MC74HC4052 MC54/74HC4053 VCC VCC VCC 16 VEE OFF A VCC VEE VIH OFF VIH 6 7 8 VEE 6 7 8 VCC COMMON O/I OFF fin N/C VOS 16 0.1F ON VEE Figure 4. Maximum Off Channel Leakage Current, Common Channel, Test Set-Up VCC 16 A VCC COMMON O/I VEE Figure 3. Maximum Off Channel Leakage Current, Any One Channel, Test Set-Up VCC OFF VCC COMMON O/I OFF NC VCC 16 ANALOG I/O dB METER ON RL CL* ANALOG I/O VIL 6 7 8 6 7 8 VEE VEE Figure 5. Maximum On Channel Leakage Current, Channel to Channel, Test Set-Up VCC VIS 0.1F VCC dB METER OFF RL Figure 6. Maximum On Channel Bandwidth, Test Set-Up VOS 16 fin *Includes all probe and jig capacitance CL* 16 RL OFF/ON RL 6 7 8 VEE VIL or VIH CHANNEL SELECT *Includes all probe and jig capacitance Figure 7. Off Channel Feedthrough Isolation, Test Set-Up VCC GND Vin 1 MHz tr = tf = 6 ns 6 7 8 VEE COMMON O/I ON/OFF ANALOG I/O RL RL CL* TEST POINT VCC 11 CHANNEL SELECT *Includes all probe and jig capacitance Figure 8. Feedthrough Noise, Channel Select to Common Out, Test Set-Up MC54/74HC4051 MC74HC4052 MC54/74HC4053 VCC VCC 16 VCC CHANNEL SELECT 50% OFF/ON GND tPLH COMMON O/I ON/OFF ANALOG I/O CL* TEST POINT tPHL ANALOG OUT 6 7 8 50% CHANNEL SELECT *Includes all probe and jig capacitance Figure 9a. Propagation Delays, Channel Select to Analog Out Figure 9b. Propagation Delay, Test Set-Up Channel Select to Analog Out VCC 16 ANALOG I/O VCC ANALOG IN COMMON O/I ON 50% CL* tPLH tPHL ANALOG OUT TEST POINT GND 6 7 8 50% *Includes all probe and jig capacitance Figure 10a. Propagation Delays, Analog In to Analog Out tf tr 90% 50% 10% ENABLE tPZL ANALOG OUT tPLZ 50% tPZH ANALOG OUT Figure 10b. Propagation Delay, Test Set-Up Analog In to Analog Out tPHZ 90% GND VCC VCC 16 1 ANALOG I/O VOH HIGH IMPEDANCE 1k ON/OFF 2 CL* VOL 50% Figure 11a. Propagation Delays, Enable to Analog Out POSITION 1 WHEN TESTING tPHZ AND tPZH POSITION 2 WHEN TESTING tPLZ AND tPZL 2 HIGH IMPEDANCE 10% 1 VCC ENABLE 6 7 8 Figure 11b. Propagation Delay, Test Set-Up Enable to Analog Out TEST POINT MC54/74HC4051 MC74HC4052 MC54/74HC4053 VCC VIS 16 RL fin A VCC 16 VOS ON COMMON O/I ON/OFF ANALOG I/O 0.1F OFF/ON NC OFF VEE RL RL CL* RL CL* 6 7 8 VEE VCC 6 7 8 11 CHANNEL SELECT *Includes all probe and jig capacitance Figure 12. Crosstalk Between Any Two Switches, Test Set-Up Figure 13. Power Dissipation Capacitance, Test Set-Up 0 VIS VCC 0.1F fin ON CL* -20 TO DISTORTION METER -30 -40 dB RL -50 DEVICE -60 6 7 8 VEE FUNDAMENTAL FREQUENCY -10 VOS 16 SOURCE -70 -80 *Includes all probe and jig capacitance -90 -100 1.0 2.0 3.125 FREQUENCY (kHz) Figure 14a. Total Harmonic Distortion, Test Set-Up Figure 14b. Plot, Harmonic Distortion APPLICATIONS INFORMATION The Channel Select and Enable control pins should be at VCC or GND logic levels. VCC being recognized as a logic high and GND being recognized as a logic low. In this example: VCC = +5V = logic high GND = 0V = logic low The maximum analog voltage swings are determined by the supply voltages VCC and VEE. The positive peak analog voltage should not exceed VCC. Similarly, the negative peak analog voltage should not go below VEE. In this example, the difference between VCC and VEE is ten volts. Therefore, using the configuration of Figure 15, a maximum analog signal of ten volts peak-to-peak can be controlled. Unused analog inputs/outputs may be left floating (i.e., not connected). However, tying unused analog inputs and outputs to VCC or GND through a low value resistor helps minimize crosstalk and feedthrough noise that may be picked up by an unused switch. Although used here, balanced supplies are not a requirement. The only constraints on the power supplies are that: VCC - GND = 2 to 6 volts VEE - GND = 0 to -6 volts VCC - VEE = 2 to 12 volts and VEE GND When voltage transients above VCC and/or below VEE are anticipated on the analog channels, external Germanium or Schottky diodes (Dx) are recommended as shown in Figure 16. These diodes should be able to absorb the maximum anticipated current surges during clipping. MC54/74HC4051 MC74HC4052 MC54/74HC4053 VCC +5V +5V 16 ANALOG SIGNAL -5V ON 6 7 8 Dx +5V ANALOG SIGNAL VCC 16 Dx Dx VEE VEE 7 8 -5V VEE Figure 15. Application Example Figure 16. External Germanium or Schottky Clipping Diodes +5V +5V 16 ANALOG SIGNAL VEE ON/OFF 6 7 8 VEE Dx ON/OFF -5V TO EXTERNAL CMOS CIRCUITRY 0 to 5V DIGITAL SIGNALS 11 10 9 VCC +5V ANALOG SIGNAL +5V * R R 11 10 9 +5V VEE +5V VEE 16 ANALOG SIGNAL ON/OFF R VEE +5V 6 7 8 LSTTL/NMOS CIRCUITRY VEE * 2K R 10K +5V ANALOG SIGNAL a. Using Pull-Up Resistors 11 10 9 LSTTL/NMOS CIRCUITRY HCT BUFFER b. Using HCT Interface Figure 17. Interfacing LSTTL/NMOS to CMOS Inputs A 11 13 LEVEL SHIFTER 14 B 10 15 LEVEL SHIFTER 12 C 9 1 LEVEL SHIFTER 5 ENABLE 6 2 LEVEL SHIFTER 4 3 Figure 18. Function Diagram, HC4051 X0 X1 X2 X3 X4 X5 X6 X7 X MC54/74HC4051 MC74HC4052 MC54/74HC4053 A 10 12 LEVEL SHIFTER 14 B 9 15 LEVEL SHIFTER 11 13 ENABLE 6 1 LEVEL SHIFTER 5 2 4 3 X0 X1 X2 X3 X Y0 Y1 Y2 Y3 Y Figure 19. Function Diagram, HC4052 A 11 13 LEVEL SHIFTER 12 14 B 10 1 LEVEL SHIFTER 2 15 C 9 3 LEVEL SHIFTER 5 4 ENABLE 6 LEVEL SHIFTER Figure 20. Function Diagram, HC4053 X1 X0 X Y1 Y0 Y Z1 Z0 Z MC54/74HC4051 MC74HC4052 MC54/74HC4053 OUTLINE DIMENSIONS J SUFFIX CERAMIC PACKAGE CASE 620-10 ISSUE V -A - 16 9 1 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIM F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. -B - L C DIM A B C D E F G J K L M N -T SEATING - PLANE K N E M F J 16 PL 0.25 (0.010) G D 16 PL 0.25 (0.010) T A M 9 1 8 T B N SUFFIX PLASTIC PACKAGE CASE 648-08 ISSUE R -A - 16 M C DIM A B C D F G H J K L M S L S -T - SEATING PLANE K H D 16 PL 0.25 (0.010) M M J G T A M D SUFFIX PLASTIC SOIC PACKAGE CASE 751B-05 ISSUE J -A - 16 -B - P 8 PL 0.25 (0.010) 8 M B M G K F R X 45 C -T SEATING - PLANE D16PL 0.25 (0.010) M M T B S A S INCHES MILLIMETERS MIN MAX MIN MAX 0.740 0.770 18.80 19.55 0.250 0.270 6.85 6.35 0.145 0.175 4.44 3.69 0.015 0.021 0.53 0.39 0.040 0.070 1.77 1.02 0.100 BSC 2.54 BSC 0.050 BSC 1.27 BSC 0.008 0.015 0.38 0.21 0.110 0.130 3.30 2.80 0.295 0.305 7.74 7.50 10 0 10 0 0.020 0.040 1.01 0.51 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 1 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 15 0 1.01 0.51 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. B F S S INCHES MIN MAX 0.750 0.785 0.240 0.295 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 15 0 0.020 0.040 J DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 4.00 3.80 1.75 1.35 0.49 0.35 1.25 0.40 1.27 BSC 0.25 0.19 0.25 0.10 7 0 6.20 5.80 0.50 0.25 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0 7 0.229 0.244 0.010 0.019 MC54/74HC4051 MC74HC4052 MC54/74HC4053 OUTLINE DIMENSIONS DW SUFFIX PLASTIC SOIC PACKAGE CASE 751G-02 ISSUE A -A- 16 9 -B- 8X P 0.010 (0.25) 1 B M M 8 16X J D 0.010 (0.25) M T A S B NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. S DIM A B C D F G J K M P R F R X 45 C -T- 14X G K 0.10 (0.004) M T U V S S S EE CC CC EE CC EE K K1 2X L/2 16 9 J1 B -U- L SECTION N-N J PIN 1 IDENT. 8 1 N 0.15 (0.006) T U S 0.25 (0.010) A -V- M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. N F DETAIL E -W- C 0.10 (0.004) -T- SEATING PLANE H D INCHES MIN MAX 0.400 0.411 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.010 0.012 0.004 0.009 0 7 0.395 0.415 0.010 0.029 DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948F-01 ISSUE O 16X K REF 0.15 (0.006) T U M SEATING PLANE MILLIMETERS MIN MAX 10.15 10.45 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 0.25 0.32 0.10 0.25 0 7 10.05 10.55 0.25 0.75 G DETAIL E DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0 8 INCHES MIN MAX 0.193 0.200 0.169 0.177 --0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0 8 MC54/74HC4051 MC74HC4052 MC54/74HC4053 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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