128M GDDR SDRAM
K4D26323QG-GC
- 1 - Rev 1.0(June 2004)
128Mbit GDDR SDRAM
Revision 1.0
June 2004
1M x 32Bit x 4 Banks
Graphic Double Data Rate
Samsung Electronics reserves the right to change products or specification without notice.
(144-Ball FBGA)
with Bi-directional Data Strobe and DLL
Synchronous DRAM
128M GDDR SDRAM
K4D26323QG-GC
- 2 - Rev 1.0(June 2004)
Revision History
Revision 1.0 (June 23, 2004)
• Changed tDQSCK/tAC of -GC22/25 from 0.55tCK to 0.45tCK
• Changed tDQSCK/tAC of -GC20 from 0. 55tCK to 0.35tCK
Revision 0.4 (June 04, 2004) - Preliminary
• Removed K4D26323QG-GC40 from the spec
• Changed VDD&VDDQ of -GC20/22 from 1.8V+0.1V to 2.0V+0.1V
• Changed AC characteristics table on page 15~ 16 from number of clock-based to ns-based. Also key parameters are
changed as below
- Changed tRFC/tWR_A/tDAL of -GC20 from 23tCK/6tCK to 25tCK/7tCK/14tCK
- Changed tRFC/tWR_A/tDAL of -GC22 from 22tCK/6tCK to 23tCK/7tCK/14tCK
- Changed tRC/tRFC /tRP/tWR_A/ tDAL of -GC25 from 17tCK/19tCK/5tCK/5tCK/10tCK to 18tCK/20tCK/6tCK/6tCK/12tCK
- Changed tRC/tRFC/tRP/tRCD/tRP/tWR_A/tDAL of -GC2A fr om 15tCK/17tCK/5tCK/5tCK/10tCK to 16tCK/18tCK/6tCK/6tCK/12tCK
- Changed tRC/tRFC/tRAS/tRP/tWR_A/tDAL of -GC33 from 13tCK/15tCK/9tCK/4tCK/4tCK to 15tCK/17tCK/10tCK/5tCK/5tCK/10tCK
• Added DC target spec
Revision 0.3 (April 22, 2004)
• Changed tCK(max) of K4D263 23QG-GC22 from 10ns to 5ns
• Changed tWR of K4D26323QG-GC20 from 6tCK to 7tCK
• Changed tWR of K4D26323QG-GC22 from 6tCK to 7tCK
• Changed tWR of K4D26323QG-GC25 from 5tCK to 6tCK
• Changed tWR of K4D26323QG-GC33 from 4tCK to 5tCK
• Changed tWR of K4D26323QG-GC40 from 3tCK to 4tCK
Revision 0.2 (April 20, 2004)
• Changed tCK(max) of K4D263 23QG-GC20 from 10ns to 5ns
Revision 0.1 (April 16, 2004)
• Typo corrected
Revision 0.0 (February 2, 2004) - Target Spec
128M GDDR SDRAM
K4D26323QG-GC
- 3 - Rev 1.0(June 2004)
The K4D26323QG is 134,217,728 bits of hyper synchronous data rate Dynamic RAM organized as 4 x1,048,576 words by
32 bits, fabricated with SAMSUNG’s high performance CMOS technology. Synchronous features with Data Strobe allow
extremely high performance up to 4.0GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of
operating frequencies, p rogrammable burst length and programmable latencies a llow the device to be useful for a variety
of high performance memory system applications.
• 1.8V ± 0.1V power supply for device operation
• 1.8V ± 0.1V power supply for I/O interface
• SSTL_18 compatible inputs/outputs
• 4 banks operation
• MRS cycle with address key programs
-. Read latency 3, 4, 5 and 6 (clock)
-. Burst le ngth (2, 4 and 8)
-. Burst type (sequential & interleave)
• All inputs except data & DM are sampled at the positive
going edge of the system clock
• Differential clock input
GENERAL DESCRIPTION
FEATURES
• No Wrtie-Interrupted by Read Function
• 4 DQS’s ( 1DQS / Byte )
• Data I/O transactions on both edges of Data strobe
• DLL aligns DQ and DQS transitions with Clock transition
• Edge aligned data & data strobe output
• Center aligned data & data strobe input
• DM for write masking only
• Auto & Self refresh
• 32ms refresh period (4K cycle)
• 144-Ball FBGA
• Maximum clock frequency up to 500MHz
• Maximum data rate up to 1.0Gbps/pin
FOR 1M x 32Bit x 4 Bank DDR SDRAM
1M x 32Bit x 4 Banks Graphic Double Data Rate Synchronous DRAM
with Bi-directional Data Strobe and DLL
ORDERING INFORMATION
* K4D26323QG-VC is the Lead Free package part number.
* For K4D26323QG-G(V)C20/22, VDD&VDDQ=2.0V +0.1V
Part NO. Max Freq. Max Data Rate Interface Package
K4D26323QG-GC20 500MHz 1000Mbps/pin
SSTL_18 144-Ball FBGA
K4D26323QG-GC22 450MHz 900Mbps/pin
K4D26323QG-GC25 400MHz 800Mbps/pin
K4D26323QG-GC2A 350MHz 700Mbps/pin
K4D26323QG-GC33 300MHz 600Mbps/pin
128M GDDR SDRAM
K4D26323QG-GC
- 4 - Rev 1.0(June 2004)
PIN CONFIGURAT ION (Top View)
PIN DESCRIPTION
CK,CK Differential Clock Input BA0, BA1 Bank Select Address
CKE Clock Enable A0 ~A11 Address Input
CS Chip Select DQ0 ~ DQ31 Data In pu t/Output
RAS Row Address Strobe VDD Power
CAS Column Address Strobe VSS Ground
WE Write Enable VDDQ Power for DQ’s
DQS Data Strobe VSSQ Ground for DQ’s
DM Data Mask NC No Connection
RFU Reserved for Future Use MCL Must Connect Low
DQS0
VSS
RFU1
Thermal VSS
Thermal VSS
Thermal VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal VSS
Thermal VSS
Thermal VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSSQ
VSSQ VSSQ VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS VSS VSS VSS
VSSVSSVSSVSS
VSS
RFU2A5
A6
DQ4
DQ6
DQ7
DQ17
DQ19
DQS2
DQ21
DQ22
CAS
RAS
CS
DM0
VDDQ
DQ5
VDDQ
DQ16
DQ18
DM2
DQ20
DQ23
WE
NC
NC
NC
VDD
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDD
NC
BA0
BA1
A0
DQ3
VDDQ
DQ31
DQ1
A10
A2
A1
VDD VDD
VDD
DQ2
VDDQ
VDD
A11
A3
A9
A4
DQ0
VDDQ
VDD
DQ29
DQ30
DQ28
VDDQ NC
VSS
A7
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDD
CK
A8/AP
DM3
VDDQ
DQ26
VDDQ
DQ15
DQ13
DM1
DQ11
DQ9
NC
CK
CKE
DQS3
DQ27
DQ25
DQ24
DQ14
DQ12
DQS1
DQ10
DQ8
NC
VREF
2345678910111213
B
C
D
E
F
G
H
J
K
L
M
N
NOTE:
1. RFU1 is reserved for A12
2. RFU2 is reserved for BA2
3. VSS Thermal balls are optional
MCL
128M GDDR SDRAM
K4D26323QG-GC
- 5 - Rev 1.0(June 2004)
INPUT/OUTPUT FUNCTIONAL DESCRIPTION
*1 : The timing reference point for the diff erential clocking is the cross point of CK and CK.
For any applications using the single ended clocking, apply VREF to CK pin.
Symbol Type Function
CK, CK*1 Input The differential system clock Input.
All of the inputs are sampled on the rising edge of the clock except
DQ’s and DM’s that are sampled on both edges of the DQS.
CKE Input Activates the CK signal wh en high and deactivates the CK signal
when low. By deactiva ting the clock, CKE low indicates the Power
down mode or Self refresh mode.
CS Input CS enable s the command decoder when lo w an d di sa bled the com-
mand decoder when high. When the command decoder is disabled,
new commands are ignored but previous operations continue.
RAS Input Latches row addresses on the positive going ed ge of the CK with
RAS low. Enables row access & precharge.
CAS Input Latches column addresses on the positive going edge of the CK with
CAS low. Enables column access.
WE Input Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
DQS0 ~ DQS3Input/Output Data input and output are synchronized with both edge of DQS.
DQS0 for DQ0 ~ DQ7, DQS1 for DQ8 ~ DQ15, DQS2 for DQ16 ~ DQ23,
DQS3 for DQ24 ~ DQ31.
DM0 ~ DM3Input Data In mask. Data In is masked by DM Latency=0 when DM is high
in burst write. DM0 for DQ0 ~ DQ7, DM1 for DQ8 ~ DQ15, DM2 for
DQ16 ~ DQ23, DM3 for DQ24 ~ DQ31.
DQ0 ~ DQ31 Input/Output Data inputs/Outputs are multiplexed on the same pins.
BA0, BA1Input Selects which bank is to be active.
A0 ~ A11 Input Row/Column addresses are multiplexed on the same pins.
Row addresses : RA0 ~ RA11, Column addresses : CA0 ~ CA7.
Column address CA8 is used for auto precharge.
VDD/VSS Power Supply Power and ground for the input buffers and core logic.
VDDQ/VSSQ Power Supply Isolated power supply and ground for the output buffers to provide
improved noise immunity.
VREF Power Supply Reference voltage for inputs, used for SSTL interface.
NC/RFU No connection/
Reserved for future use This pin is recommended to be left "No connection" on the device
MCL Must Connect Low Must connect low
128M GDDR SDRAM
K4D26323QG-GC
- 6 - Rev 1.0(June 2004)
BLOCK DIAGRAM (1Mbit x 32I/O x 4 Bank)
Bank Select
Timing Register
Address Register
Refresh Counter
Row Buffer
Row Decoder Col. Buffer
Data Input Register
Serial to parallel
1Mx32
1Mx32
1Mx32
1Mx32
Sense AMP
2-bit prefetch
Output BufferI/O Control
Column Decoder
Latency & Burst Length
Programming Register
Strobe
Gen.
CK,CK
ADDR
LCKE
CK,CK CKE CS RAS CAS WE DMi
LDMi
CK,CK
LCAS
LRAS LCBR LWE LWCBR
LRAS
LCBR
CK, CK
64
64 32
32
LWE
LDMi
x32
DQi
Data Strobe
Intput Buffer
DLL (DQS0~DQS3)
128M GDDR SDRAM
K4D26323QG-GC
- 7 - Rev 1.0(June 2004)
• Power-Up Sequence
DDR SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.
1. Apply power and keep CKE at low state (All other inputs may be undefined)
- Apply VDD before VDDQ .
- Apply VDDQ before VREF & VTT
2. Start clock and maintain stable condition for minimum 200us.
3. The minimum of 200us after stable power and clock(CK,CK ), apply NOP and take CKE to be high .
4. Issue precharge command for all banks of the device.
5. Issue a EMRS command to enable DLL. Minimum 20 clcok cycles are required prior to MRS command.
*1 6. Issue a MRS command to reset DLL. The additional 200 clock cycles are required to lock the DLL.
*1,2 7. Issue precharge command for all banks of the device.
8. Issue at least 2 or more auto-refresh commands.
9. Issue a mode register set command with A8 to low to initialize the mode register.
*1 The additional 200cycles of clock input is required to lock the DLL after enabling DLL.
*2 Sequence of 6&7 is rega rdless of the order
FUNCTIONAL DESCRIPTION
Power up & Initialization Sequence
Command tRP 4 Clock min.
precharge
ALL Banks 2nd Auto
Refresh Mode
Register Set Any
Command
tRFC
1st Auto
Refresh
tRFC
EMRS MRS
20 Clock min.
DLL Reset
precharge
ALL Banks
tRP
Inputs must be
stable fo r 200us
~
~
200 Clock min.
4 Clock min.
CK,CK
* When the operating frequency is changed, DLL reset should be required again.
After DLL reset again, the minimum 200 cycles of clock input is needed to lock the DLL.
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
128M GDDR SDRAM
K4D26323QG-GC
- 8 - Rev 1.0(June 2004)
The mode register stores the data for controlling the variou s operating modes of DDR SDRAM. It programs CAS latency,
128M GDDR SDRAM
K4D26323QG-GC
- 13 - Rev 1.0(June 2004)
AC CHARACTERISTICS (I)
Parameter Symbol -20 -22 -25 -2A -33 Unit Note
Min Max Min Max Min Max Min Max Min Max
CK cycle time
CL=3
tCK
-
5.0
-
5.0
-
10.0
-
10.0
-
10.0
ns
CL=4----3.3ns
CL=5 - - 2.5 2.86 - ns
CL=6 2.0 2.2 - - - ns
CK high level width tCH 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK
CK low level width tCL 0.4 5 0 .55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK
DQS out access time from CK tDQSCK -0.35 0.35 -0.45 0.45 -0.45 0.45 -0.55 0.55 -0.55 0.55 ns
Output access time from CK tAC -0.35 0.35 -0.45 0.45 -0.45 0.45 -0.55 0.55 -0.55 0.55 ns
Data strobe edge to D out edge tDQSQ - 0.25 - 0.28 - 0.28 - 0.35 - 0.35 ns 1
Read preamble tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 tCK
Read postamble tRPST 0.4 0.6 0.4 0.6 0.4 0 .6 0.4 0.6 0.4 0.6 tCK
CK to valid DQS-in tDQSS 0.85 1.15 0.85 1.15 0.85 1.15 0.85 1.15 0.85 1.15 tCK
DQS-In setup time tWPRES0-0-0-0-0-ns
DQS-in hold time tWPREH 0.35 - 0.35 - 0.35 - 0.35 - 0.35 - tCK
DQS write postamble tWPST 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK
DQS-In high level width tDQSH 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK
DQS-In low level width tDQSL 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK
Address and Control input setup tIS 0.5 - 0.55 - 0.6 - 0.8 - 0.8 - ns
Address and Control input hold tIH 0.5 - 0.55 - 0.6 - 0.8 - 0.8 - ns
DQ and DM setup time to DQS tDS 0.25 - 0.27 - 0.3 - 0.35 - 0.35 - ns
DQ and DM hold time to DQS tDH 0.25 - 0.27 - 0.3 - 0.35 - 0.35 - ns
Clock half period tHP tCLmin
or
tCHmin -tCLmin
or
tCHmin -tCLmin
or
tCHmin -tCLmin
or
tCHmin -tCLmin
or
tCHmin -ns1
Data Hold skew factor tQHS - 0.4 - 0.4 - 0.4 - 0.4 - 0.4 ns
Data output hold time from DQS tQH tHP-
tQHS -tHP-
tQHS -tHP-
tQHS -tHP-
tQHS -tHP-
tQHS -ns1
13467
tCL
tCK
CK, CK
DQS
DQ
CS
DM
25
tIS
tIH
8
tDS tDH
01
tRPST
tRPRE
Db0 Db1
tDQSS tDQSH tDQSL
tCH
Qa1 Qa2
COMMAND READA WRITEB
tDQSQ tWPRES
tWPREH
tDQSCK
tAC
Simplified Timing @ BL=2, CL=4
128M GDDR SDRAM
K4D26323QG-GC
- 14 - Rev 1.0(June 2004)
Note 1 :
- The JEDEC DDR specification currently defines the output data valid window(tDV) as the time period when the data
strobe and all data associated with that data strobe are coincidentally valid.
- The previously used definition of tDV(=0.35tCK) artificially penalizes system timing budgets by assuming the worst case
output vaild window even then the clock duty cycle applied to the device is better than 45/55%
- A new AC timing term, tQH which stands for data output hold time from DQS is difined to account for clock duty cycle
variation and replaces tDV
- tQHmin = tHP-X where
. tHP=Minimum half clock period for any given cycle and is defined by clock high or clock low time(tCH,tCL)
. X=A frequency dependent timing allowance account for tDQSQmax
tQH Timing (CL4, BL2)
1tHP
CK, CK
DQS
DQ
CS
25
01
COMMAND READA
tQH
Qa0
tDQSQ(max)
tDQSQ(max)
34
Qa1
VALID NOP NOP NOP NOP NOP NOP VALID
tIS
tIS
CK, CK
CKE
Command
Exit Powr Down mode
Enter Power Down mode
(Read or Write operation
must not be in progress)
3tCK
Power Down Timing
128M GDDR SDRAM
K4D26323QG-GC
- 15 - Rev 1.0(June 2004)
AC CHARACTERISTICS (II)
Note : 1. For normal write operation, even numbers of Din are to be written inside DRAM
Parameter Symbol -20 -22 -25 -2A -33 Unit Note
Min Max Min Max Min Max Min Max Min Max
Row cycle time tRC 46 - 46.2 - 45 - 45.8 - 49.5 - ns
Refresh row cycle time tRFC 50 - 50.6 - 50 - 51.5 - 56.1 - ns
Row active time tRAS 32 100K 30.8 100K 30 100K 28.6 100K 33 100K ns
RAS to CAS delay for Read tRCDRD 14 - 15.4 - 15 - 16.5 - 16.5 - ns
RAS to CAS delay for Write tRCDWR 10 - 11 - 10 - 11.4 - 11.4 - ns
Row precharge time tRP 14 - 15.4 - 15 - 16.5 - 16.5 - ns
Last data in to Row prec harge
@Normal Precharge tWR 14 - 15.4 - 15 - 16.5 - 16.5 - ns 1
Last data in to Row prec harge
@Auto Precharge tWR_A 14 - 15.4 - 15 - 16.5 - 16.5 - ns 1
Auto precharge write recovery +
Precharge tDAL 28 - 30.8 - 30 - 33 - 33 - ns
Row active to Row active tRRD 5 - 5 - 4 - 4 - 3 - tCK
Last data in to Read command tCDLR 2 - 2 - 2 - 2 - 2 - tCK 1
Col. address to Col. address tCCD 1 - 1 - 1 - 1 - 1 - tCK
Mode register set cycle time tMRD 5 - 5 - 4 - 3 - 3 - tCK
Exit self refresh to read command tXSR 200 - 200 - 200 - 200 - 200 - tCK
Power down exit time tPDEX 3tCK+
tIS -3tCK+
tIS -3tCK+
tIS -3tCK+
tIS -3tCK+
tIS -ns
Refresh interval time tREF 7.8 - 7.8 - 7. 8 - 7.8 - 7.8 - us
128M GDDR SDRAM
K4D26323QG-GC
- 16 - Rev 1.0(June 2004)
AC CHARACTERISTICS (III)
K4D26323QG-GC20
Frequency Cas Latency tRC tRFC tRAS tRCDRD tRCDWR tRP tRRD tDAL Unit
500MHz ( 2.0ns ) 6 23 25 16 7 5 7 5 14 tCK
450MHz ( 2.2ns ) 6 21 23 14 7 5 7 5 14 tCK
K4D26323QG-GC22
Frequency Cas Latency tRC tRFC tRAS tRCDRD tRCDWR tRP tRRD tDAL Unit
450MHz ( 2.2ns ) 6 21 23 14 7 5 7 5 14 tCK
K4D26323QG-GC25
Frequency Cas Latency tRC tRFC tRAS tRCDRD tRCDWR tRP tRRD tDAL Unit
400MHz ( 2.5ns ) 5 18 20 12 6 4 6 4 12 tCK
350MHz ( 2.86ns ) 5 16 18 10 6 4 6 4 12 tCK
300MHz ( 3.3ns ) 4 15 17 10 5 3 5 3 10 tCK
K4D26323QG-GC2A
Frequency Cas Latency tRC tRFC tRAS tRCDRD tRCDWR tRP tRRD tDAL Unit
350MHz ( 2.86ns ) 5 16 18 10 6 4 6 4 12 tCK
300MHz ( 3.3ns ) 4 15 17 10 5 3 5 3 10 tCK
K4D26323QG-GC33
Frequency Cas Latency tRC tRFC tRAS tRCDRD tRCDWR tRP tRRD tDAL Unit
300MHz ( 3.3ns ) 4 15 17 10 5 3 5 3 10 tCK
(Unit : Number of Clock)
128M GDDR SDRAM
K4D26323QG-GC
- 17 - Rev 1.0(June 2004)
012345678
BAa
Ra
Ra
tRCD
ACTIVEA ACTIVEB WRITEA WRITEB
13 14 15 16 17 18 19 20 21
BAa BAb
Ca Cb
BAa
Ca
9101112
PRECH
BAa
22
Ra
Normal Write Burst
(@ BL=4) Multi Bank Interleaving Write Burst
(@ BL=4)
BAa
Ra
Ra
BAb
Rb
Rb
tRAS
tRC
tRP
tRRD
COMMAND
DQS
DQ
WE
DM
CK, CK
A8/AP
ADDR
(A0~A7,
BA[1:0]
A9,A10)
ACTIVEA WRITEA
Da0 Da1 Da2 Da3
Simplified Timing(2) @ BL=4
Db0 Db1 Db3
Da0 Da1 Da2 Da3 Db2
128M GDDR SDRAM
K4D26323QG-GC
- 18 - Rev 1.0(June 2004)
PACKAGE DIMENSIONS (144-Ball FBGA)
Unit : mm
12.0
12.0
0.8
0.8
0.35 ± 0.05
1.40 Max
<Top View>
<Bottom View>
0.45 ± 0.05
0.8x11=8.8
0.40
0.8x11=8.8
0.40
B
C
D
E
F
G
H
J
K
L
M
N13 12 11 10 9 8 7 6 5 4 3 2
A1 INDEX MARK
A1 INDEX MARK
0.10 Max
