June 1996
NDT452AP
P-Channel Enhancement Mode Field Effect Transistor
General Description Features
________________________________________________________________________________
Absolute Maximum Ratings TA = 25°C unless otherwise noted
Symbol Parameter NDT452AP Units
VDSS Drain-Source Voltage -30 V
VGSS Gate-Source Voltage ±20 V
IDDrain Current - Continuous (Note 1a) -5 A
- Pulsed - 15
PDMaximum Power Dissipation (Note 1a) 3W
(Note 1b) 1.3
(Note 1c) 1.1
TJ,TSTG Operating and Storage Temperature Range -65 to 150 °C
THERMAL CHARACTERISTICS
RθJA Thermal Resistance, Junction-to-Ambient (Note 1a) 42 °C/W
RθJC Thermal Resistance, Junction-to-Case (Note 1) 12 °C/W
* Order option J23Z for cropped center drain lead.
NDT452AP Rev. B1
-5A, -30V. RDS(ON) = 0.065 @ VGS = -10V
RDS(ON) = 0.1 @ VGS = -4.5V.
High density cell design for extremely low RDS(ON).
High power and current handling capability in a widely used
surface mount package.
Power SOT P-Channel enhancement mode power field
effect transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state resistance
and provide superior switching performance. These devices
are particularly suited for low voltage applications such as
notebook computer power management and DC motor
control.
D
DS
G
D
S
G
© 1997 Fairchild Semiconductor Corporation
Electrical Characteristics (TA = 25°C unless otherwise noted)
Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS
BVDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = -250 µA -30 V
IDSS Zero Gate Voltage Drain Current VDS = -24 V, VGS = 0 V -1 µA
TJ = 55°C -10 µA
IGSSF Gate - Body Leakage, Forward VGS = 20 V, VDS = 0 V 100 nA
IGSSR Gate - Body Leakage, Reverse VGS = -20 V, VDS= 0 V -100 nA
ON CHARACTERISTICS (Note 2)
VGS(th) Gate Threshold Voltage VDS = VGS, ID = -250 µA -1 -1.6 -2.8 V
TJ = 125°C -0.7 -1.2 -2.2
RDS(ON) Static Drain-Source On-Resistance VGS = -10 V, ID = -5.0 A 0.052 0.065
TJ = 125°C 0.075 0.13
VGS = -4.5 V, ID = -4.3 A 0.085 0.1
ID(on) On-State Drain Current VGS = -10 V, VDS = -5 V -15 A
VGS = -4.5 V, VDS = -5 V -5
gFS Forward Transconductance VDS = -10 V, ID = -5.0 A 7S
DYNAMIC CHARACTERISTICS
Ciss Input Capacitance VDS = -15 V, VGS = 0 V,
f = 1.0 MHz 690 pF
Coss Output Capacitance 430 pF
Crss Reverse Transfer Capacitance 160 pF
SWITCHING CHARACTERISTICS (Note 2)
tD(on)Turn - On Delay Time VDD = -10 V, ID = -1 A,
VGEN = -10 V, RGEN = 6 9 20 ns
trTurn - On Rise Time 20 30 ns
tD(off) Turn - Off Delay Time 40 50 ns
tfTurn - Off Fall Time 19 40 ns
QgTotal Gate Charge VDS = -10 V,
ID = -5.0 A, VGS = -10 V 22 30 nC
Qgs Gate-Source Charge 3.2 nC
Qgd Gate-Drain Charge 5.2 nC
NDT452AP Rev. B1
Electrical Characteristics (TA = 25°C unless otherwise noted)
Symbol Parameter Conditions Min Typ Max Units
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
ISMaximum Continuous Drain-Source Diode Forward Current -2.5 A
VSD Drain-Source Diode Forward Voltage VGS = 0 V, IS = -2.5 A (Note 2) -0.85 -1.2 V
trr Reverse Recovery Time VGS = 0 V, IF = -2.5 A, dIF/dt = 100 A/µs 100 ns
Notes:
1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by
design while RθCA is determined by the user's board design.
PD(t)=TJTA
RθJA(t)=TJTA
RθJC+RθCA(t)=ID
2(t)×RDS(ON)TJ
Typical RθJA using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
a. 42oC/W when mounted on a 1 in2 pad of 2oz copper.
b. 95oC/W when mounted on a 0.066 in2 pad of 2oz copper.
c. 110oC/W when mounted on a 0.0123 in2 pad of 2oz copper.
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
NDT452AP Rev. B1
1a 1b 1c
NDT452AP Rev. B1
-4-3-2-10
-20
-15
-10
-5
0
V , DRAIN-SOURCE VOLTAGE (V)
I , DRAIN-SOURCE CURRENT (A)
V = -10V
GS
DS
D
-4.0
-6.0 -5.0
-3.5
-3.0
-4.5
-50 -25 0 25 50 75 100 125 150
0.6
0.8
1
1.2
1.4
1.6
T , JUNCTION TEMPERATURE (°C)
DRAIN-SOURCE ON-RESISTANCE
J
V = -10V
GS
I = -5.0A
D
R , NORMALIZED
DS(ON)
-50 -25 025 50 75 100 125 150
0.6
0.7
0.8
0.9
1
1.1
1.2
T , JUNCTION TEMPERATURE (°C)
GATE-SOURCE THRESHOLD VOLTAGE
I = -250µA
D
V = V
DS GS
J
V , NORMALIZED
th
-20-16-12-8-40
0.5
1
1.5
2
2.5
3
I , DRAIN CURRENT (A)
DRAIN-SOURCE ON-RESISTANCE
D
R , NORMALIZED
DS(on)
V = -3.5V
GS
-10
-5.0
-6.0
- 4.0
-4.5
Typical Electrical Characteristics
Figure 1. On-Region Characteristics. Figure 2. On-Resistance Variation with Gate
Voltage and Drain Current.
Figure 3. On-Resistance Variation with
Temperature. Figure 4. On-Resistance Variation with Drain
Current and Temperature.
Figure 5. Transfer Characteristics. Figure 6. Gate Threshold Variation with
Temperature.
-6-5-4-3-2-1
-20
-15
-10
-5
0
V , GATE TO SOURCE VOLTAGE (V)
I , DRAIN CURRENT (A)
V = -10V
DS
GS
D
T = -55°C
J
25°C
125°C
-20-16-12-8-40
0.5
1
1.5
2
I , DRAIN CURRENT (A)
DRAIN-SOURCE ON-RESISTANCE
D
R , NORMALIZED
DS(on)
V = -10V
GS
T = 125°C
J
25°C
-55°C
NDT452AP Rev. B1
-50 -25 025 50 75 100 125 150
0.94
0.96
0.98
1
1.02
1.04
1.06
1.08
1.1
T , JUNCTION TEMPERATURE (°C)
DRAIN-SOURCE BREAKDOWN VOLTAGE
I = -250µA
D
BV , NORMALIZED
DSS
J00.4 0.8 1.2 1.6 2
0.001
0.01
0.1
1
5
10
20
-V , BODY DIODE FORWARD VOLTAGE (V)
-I , REVERSE DRAIN CURRENT (A)
T = 125°C
J25°C -55°C
V = 0V
GS
SD
S
0 5 10 15 20 25
0
2
4
6
8
10
Q , GATE CHARGE (nC)
-V , GATE-SOURCE VOLTAGE (V)
g
GS
I = -5.0A
DV = -5V
DS -10V -20V
0.1 0.2 0.5 1 2 5 10 30
100
200
300
500
1000
2000
-V , DRAIN TO SOURCE VOLTAGE (V)
CAPACITANCE (pF)
DS
C
iss
f = 1 MHz
V = 0V
GS
C
oss
C
rss
Figure 7. Breakdown Voltage Variation with
Temperature. Figure 8. Body Diode Forward Voltage Variation
with Current and Temperature.
Figure 9. Capacitance Characteristics. Figure 10. Gate Charge Characteristics.
Typical Electrical Characteristics
D
S
-VDD
RL
VOUT
VGS DUT
VIN
RGEN G
Figure 11. Switching Test Circuit. Figure 12. Switching Waveforms.
10%
50%
90%
10%
90%
90%
50%
VIN
VOUT
on off
d(off) f
r
d(on)
t t
ttt
t
INVERTED
10%
PULSE WIDTH
NDT452AP Rev. B1
Typical Thermal Characteristics
-20-16-12-8-40
0
3
6
9
12
I , DRAIN CURRENT (A)
g , TRANSCONDUCTANCE (SIEMENS)
T = -55°C
J
25°C
D
FS
V = -10V
DS
125°C
Figure 13. Transconductance Variation with Drain
Current and Temperature.
00.2 0.4 0.6 0.8 1
0.5
1
1.5
2
2.5
3
3.5
2oz COPPER MOUNTING PAD AREA (in )
STEADY-STATE POWER DISSIPATION (W)
2
1c
1b
1a
4.5"x5" FR-4 Board
T = 25 C
Still Air
Ao
Figure 14. SOT-223 Maximum Steady- tate
Power Dissipation versus Copper
Mounting Pad Area.
Figure 16. Maximum Safe Operating Area.
00.2 0.4 0.6 0.8 1
2
3
4
5
6
2oz COPPER MOUNTING PAD AREA (in )
I , STEADY-STATE DRAIN CURRENT (A)
2
1c
1b
1a
4.5"x5" FR-4 Board
T = 25 C
Still Air
V = -10V
Ao
GS
D
0.1 0.2 0.5 1 2 5 10 30 50
0.01
0.05
0.1
0.5
1
5
10
20
50
- V , DRAIN-SOURCE CURRENT (V)
-I , DRAIN CURRENT (A)
DS
D
10ms
100ms
10s
1s
DC
100us
1ms
RDS(ON) LIMIT
V = -10V
SINGLE PULSE
R = See Note 1c
T = 25°C
GS
A
θJA
Figure 15. Maximum Steady-State Drain
Current versus Copper Mounting Pad
Area.
Figure 17. Transient Thermal Response Curve.
Note: Thermal characterization performed using the conditions described in note 1c. Transient thermal response will change
depending on the circuit board design.
0.0001 0.001 0.01 0.1 1 10 100 300
0.001
0.002
0.005
0.01
0.02
0.05
0.1
0.2
0.5
1
t , TIME (sec)
TRANSIENT THERMAL RESISTANCE
r(t), NORMALIZED EFFECTIVE
1
Single Pulse
D = 0.5
0.1
0.05
0.02
0.01
0.2
Duty Cycle, D = t / t
12
R (t) = r(t) * R
R = See Note 1 c
θJA
θJA
θJA
T - T = P * R (t)
θJA
A
J
P(pk)
t
1 t
2