Filterless, High Efficiency,
Mono 2.8 W, Class-D Audio Amplifier
Data Sheet SSM2305
Rev. B Document Feedback
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FEATURES
Filterless Class-D amplifier with Σ-Δ modulation
No sync necessary when using multiple Class-D amplifiers
from Analog Devices, Inc.
2.8 W into 4 Ω load and 1.6 W into 8 Ω load at 5.0 V supply
with <10% total harmonic distortion (THD)
89% efficiency at 5.0 V, 1.3 W into 8 Ω speaker
>98 dB signal-to-noise ratio (SNR)
Single-supply operation from 2.5 V to 5.5 V
20 nA ultralow shutdown current
Short-circuit and thermal protection
Available in 8-lead, 3 mm × 3 mm LFCSP and MSOP
Pop-and-click suppression
Built-in resistors reduce board component count
Fixed and user-adjustable gain configurations
APPLICATIONS
Mobile phones
MP3 players
Portable gaming
Portable electronics
Educational toys
GENERAL DESCRIPTION
The SSM2305 is a fully integrated, high efficiency, Class-D
audio amplifier designed to maximize performance for mobile
phone applications. The application circuit requires a minimum
of external components and operates from a single 2.5 V to 5.5 V
supply. It is capable of delivering 2.2 W of continuous output
power with less than 1% THD + N driving a 4 Ω load from a
5.0 V supply. It has built-in thermal shutdown and output short-
circuit protection.
The SSM2305 features a high efficiency, low noise modulation
scheme that does not require external LC output filters. The modu-
lation provides high efficiency even at low output power. The
SSM2305 operates with 90% efficiency at 1.3 W into 8 Ω or 83%
efficiency at 2.2 W into 4 Ω from a 5.0 V supply and has an SNR of
>98 dB. Spread-spectrum pulse density modulation is used to
provide lower EMI-radiated emissions compared with other
Class-D architectures.
The SSM2305 has a micropower shutdown mode with a maximum
shutdown current of 30 nA. Shutdown is enabled by applying
a Logic 0 to the SD pin. The device also includes pop-and-click
suppression circuitry. This minimizes voltage glitches at the
output during turn-on and turn-off, thus reducing audible noise
on activation and deactivation.
The fully differential input of the SSM2305 provides excellent
rejection of common-mode noise on the input. Input coupling
capacitors can be omitted if the dc input common-mode voltage
is approximately VDD/2.
The SSM2305 has excellent rejection of power supply noise,
including noise caused by GSM transmission bursts and RF
rectification. PSRR is typically 60 dB at 217 Hz.
The default gain of the SSM2305 is 18 dB, but users can reduce the
gain by using a pair of external resistors.
The SSM2305 is specified over the commercial temperature range
(−40°C to +85°C). It is available in both an 8-lead, 3 mm × 3 mm
lead frame chip scale package (LFCSP) and an 8-lead mini small
outline package (MSOP).
FUNCTIONAL BLOCK DIAGRAM
07243-001
SHUTDOWN
0.1µF
VDD
POP/CLICK
SUPPRESSION
OUT+
OUT–
IN+
VBATT
2.5V TO 5.5V
IN–
MODULATOR
(Σ-∆)
GND
10µF
47nF*
*
INPUT CAPACITORS ARE OPTIONAL IF INPUT DC COMMON-MODE VOLTAGE IS
APPROXIMATELY
V
DD/2.
47nF*
SD
AUDIO IN–
AUDIO IN+
SSM2305
37kΩ
296kΩ
296kΩ
37kΩ
FET
DRIVER
BIAS INTERNAL
OSCILLATOR
Figure 1.
SSM2305* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
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EVALUATION KITS
•SSM2305 Evaluation Board
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•SSM2305: Filterless, High Efficiency, Mono 2.8 W, Class-D
Audio Amplifier Data Sheet
DESIGN RESOURCES
•SSM2305 Material Declaration
•PCN-PDN Information
•Quality And Reliability
•Symbols and Footprints
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SSM2305 Data Sheet
Rev. B | Page 2 of 16
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 4
Thermal Resistance ...................................................................... 4
ESD Caution .................................................................................. 4
Pin Configurations and Function Descriptions ........................... 5
Typical Performance Characteristics ............................................. 6
Applications Information .............................................................. 11
Overview ..................................................................................... 11
Gain .............................................................................................. 12
Pop-and-Click Suppression ...................................................... 12
Output Modulation Description .............................................. 12
Layout .......................................................................................... 12
Input Capacitor Selection .......................................................... 12
Proper Power Supply Decoupling ............................................ 13
Outline Dimensions ....................................................................... 14
Ordering Guide .......................................................................... 14
REVISION HISTORY
5/2016—Rev. A to Rev. B
Changed CP-8-2 to CP-8-13 ........................................ Throughout
Changes to Figure 2 and Table 4 ..................................................... 5
Updated Outline Dimensions ....................................................... 14
Changes to Ordering Guide .......................................................... 14
7/2008—Rev. 0 to Rev. A
Changes to Figure 1 .......................................................................... 1
Change to Shutdown Current Parameter, Table 1 ........................ 3
Change to Differential Input Impedance Parameter, Table 1 ..... 3
Added Exposed Pad Notation to Figure 2 ..................................... 5
Change to Figure 24 ......................................................................... 9
Changes to Figure 32 and Figure 33 ............................................. 11
Changes to Gain Section ................................................................ 12
Updated Outline Dimensions ....................................................... 14
3/2008—Revision 0: Initial Version
Data Sheet SSM2305
Rev. B | Page 3 of 16
SPECIFICATIONS
VDD = 5.0 V, TA = 25oC, RL = 8 Ω + 33 μH, unless otherwise noted.
Table 1.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
DEVICE CHARACTERISTICS
Output Power PO RL = 8 Ω, THD = 1%, f = 1 kHz, BW = 20 kHz 1.34 W
R
L = 8 Ω, THD = 1%, f = 1 kHz, BW = 20 kHz, VDD = 3.6 V 0.68 W
R
L = 8 Ω, THD = 10%, f = 1 kHz, BW = 20 kHz 1.67 W
R
L = 8 Ω, THD = 10%, f = 1 kHz, BW = 20 kHz, VDD = 3.6 V 0.85 W
R
L = 4 Ω, THD = 1%, f = 1 kHz, BW = 20 kHz 2.22 W
R
L = 4 Ω, THD = 1%, f = 1 kHz, BW = 20 kHz, VDD = 3.6 V 1.1 W
R
L = 4 Ω, THD = 10%, f = 1 kHz, BW = 20 kHz 2.8 W
R
L = 4 Ω, THD = 10%, f = 1 kHz, BW = 20 kHz, VDD = 3.6 V 1.3 W
Efficiency η PO = 1.3 W, 8 Ω 89 %
Total Harmonic Distortion + Noise THD + N PO = 1 W into 8 Ω, f = 1 kHz 0.02 %
P
O = 0.5 W into 8 Ω, f = 1 kHz, VDD = 3.6 V 0.02 %
Input Common-Mode Voltage Range VCM 1.0 VDD − 1 V
Common-Mode Rejection Ratio CMRRGSM VCM = 2.5 V ± 100 mV at 217 Hz, output referred 55 dB
Average Switching Frequency fSW 280 kHz
Differential Output Offset Voltage VOOS G = 18 dB 2.0 mV
POWER SUPPLY
Supply Voltage Range VDD Guaranteed from PSRR test 2.5 5.5 V
Power Supply Rejection Ratio PSRR VDD = 2.5 V to 5.0 V, dc input floating 70 85 dB
PSRRGSM VRIPPLE = 100 mV at 217 Hz, inputs ac GND, CIN = 0.1 μF 60 dB
Supply Current ISY VIN = 0 V, no load 3.2 mA
V
IN = 0 V, 3.3 mA
V
IN = 0 V, no load, VDD = 3.6 V 2.8 mA
V
IN = 0 V, VDD = 3.6 V 2.9 mA
V
IN = 0 V, no load, VDD = 2.5 V 2.4 mA
V
IN = 0 V, VDD = 2.5 V 2.4 mA
Shutdown Current ISD SD = GND 20 30 nA
GAIN CONTROL
Closed-Loop Gain Av 18 dB
Differential Input Impedance ZIN SD = VDD 37 kΩ
SHUTDOWN CONTROL
Input Voltage High VIH ISY ≥ 1 mA 1.2 V
Input Voltage Low VIL ISY ≤ 300 nA 0.5 V
Wake-Up Time tWU SD rising edge from GND to VDD 30 ms
Shutdown Time tSD SD falling edge from VDD to GND 5 μs
Output Impedance ZOUT SD = GND >100 kΩ
NOISE PERFORMANCE
Output Voltage Noise en VDD = 3.6 V, f = 20 Hz to 20 kHz, inputs are ac grounded,
AV = 18 dB, A-weighted
40 μV
Signal-to-Noise Ratio SNR PO = 1.4 W, RL = 8 Ω 98 dB
SSM2305 Data Sheet
Rev. B | Page 4 of 16
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings apply at TA = 25°C, unless other-
wise noted.
Table 2.
Parameter Rating
Supply Voltage 6 V
Input Voltage VDD
Common-Mode Input Voltage VDD
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +85°C
Junction Temperature Range −65°C to +165°C
Lead Temperature (Soldering, 60 sec) 300°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 3.
Package Type θJA θ
JC Unit
8-Lead, 3 mm × 3 mm LFCSP 62 20.8 °C/W
8-Lead MSOP 210 45 °C/W
ESD CAUTION
Data Sheet SSM2305
Rev. B | Page 5 of 16
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
NOTES:
1. NC = NO CONNECT.
2. EXPOSED PAD IS NOT CONNECTED INTERNALLY.
FOR INCREASED RELIABILITY OF THE SOLDER
JOINTS AND MAXIMUM THERMAL CAPABILITY IT
IS RECOMMENDED THAT THE PAD BE SOLDERED
TO THE GROUND PLANE.
SD
NC
IN+
IN–
GND
OUT–
VDD
OUT+
0
7243-002
3
4
1
2
6
5
8
7
SSM2305
TOP VIEW
(Not to Scale)
Figure 2. LFSCP Pin Configuration
SD
1
NC
2
IN
+
3
IN–
4
OUT–
8
GND
7
VDD
6
OUT+
5
SSM2305
TOP VIEW
(Not to Scale)
07243-103
NC = NO CONNECT
Figure 3. MSOP Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic Description
LFCSP MSOP
1 1 SD Shutdown Input. Active low digital input.
2 2 NC No Connect. This pin has no function; tie it to GND.
3 3 IN+ Noninverting Input.
4 4 IN− Inverting Input.
5 5 OUT+ Noninverting Output.
6 6 VDD Power Supply.
7 7 GND Ground.
8 8 OUT− Inverting Output.
0 N/A1 EPAD Exposed Pad. The exposed pad is not connected internally. For increased reliability of the solder joints and
maximum thermal capability it is recommended that the pad be soldered to the ground plane.
1 N/A means not applicable.
SSM2305 Data Sheet
Rev. B | Page 6 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
100
10
1
0.1
0.01
0.0001 100.001
THD + N ( %)
0.01 0.1 1
OUTPUT POW ER (W)
07243-004
VDD = 2.5V
VDD = 5V
VDD = 3.6V
RL = 4Ω + 33µH
GAI N = 18dB
Figure 4. THD + N vs. Output Power into 4 Ω + 33 μH, AV = 18 dB
100
10
1
0.1
0.01
0.001
0.0001 100.001 0.01 0.1 1
OUTPUT POW ER (W)
07243-005
VDD = 2.5V
RL = 4Ω + 33µH
GAI N = 6dB
VDD = 5V
VDD = 3.6V
THD + N ( %)
Figure 5. THD + N vs. Output Power into 4 Ω + 33 μH, AV = 6 dB
100
10
1
0.1
0.01
0.001
0.0001 100.001 0.01 0.1 1
OUTPUT POW ER (W)
07243-006
RL = 8Ω + 33µH
GAI N = 18dB
THD + N ( %)
VDD = 2.5V
VDD = 5V
VDD = 3.6V
Figure 6. THD + N vs. Output Power into 8 Ω + 33 μH, AV = 18 dB
100
10
1
0.1
0.01
0.001
0.0001 100.001 0.01 0.1 1
OUTPUT POW ER (W)
07243-007
VDD = 2.5V
RL = 8Ω + 33µH
GAI N = 6dB
VDD = 5V
THD + N ( %)
VDD = 3.6V
Figure 7. THD + N vs. Output Power into 8 Ω + 33 μH, AV = 6 dB
100
10
1
0.1
0.01
0.00110 100
THD + N ( %)
1000 100000
10000
07243-008
0.5W
2W
V
DD
= 5V
GAI N = 18dB
RL = 4Ω + 33µH
1W
FREQUENCY ( Hz )
Figure 8. THD + N vs. Frequency, VDD = 5 V, RL = 4 Ω + 33 μH, AV = 18 dB
100
10
1
0.1
0.01
0.001
100
10
1
0.1
0.01
0.00110 100
THD + N ( %)
1000 10000010000
FREQUENCY ( Hz )
07243-009
0.25W
0.5W
V
DD
= 5V
GAI N = 18dB
R
L
= 8Ω + 33µH
1W
Figure 9. THD + N vs. Frequency, VDD = 5 V, RL = 8 Ω + 33 μH, AV = 18 dB
Data Sheet SSM2305
Rev. B | Page 7 of 16
100
10
1
0.1
0.01
0.00110 100
THD + N ( %)
1000 100000
10000
07243-010
1W
V
DD
= 3.6V
GAI N = 18dB
R
L = 4Ω + 33µH
0.5W
FREQUENCY ( Hz )
0.25W
Figure 10. THD + N vs. Frequency, VDD = 3.6 V, RL = 4 Ω + 33 μH, AV = 18 dB
100
10
1
0.1
0.01
0.00110 100
THD + N ( %)
1000 100000
10000
07243-011
V
DD
= 3.6V
GAI N = 18dB
R
L
= 8Ω + 33µH
0.5W 0.25W
0.25W
FREQUENCY ( Hz )
Figure 11. THD + N vs. Frequency, VDD = 3.6 V, RL = 8 Ω + 33 μH, AV = 18 dB
100
10
1
0.1
0.01
0.00110 100
THD + N ( %)
1000 10000010000
07243-012
V
DD
= 2.5V
GAI N = 18dB
R
L
= 4Ω + 33µH
0.5W
0.25W
0.125W
FREQUENCY ( Hz )
Figure 12. THD + N vs. Frequency, VDD = 2.5 V, RL = 4 Ω + 33 μH, AV = 18 dB
100
10
1
0.1
0.01
0.00110 100
THD + N ( %)
1000 10000010000
07243-013
V
DD
= 2.5V
GAI N = 18dB
R
L
= 8Ω + 33µH
0.25W
0.075W
0.125W
FREQUENCY ( Hz )
Figure 13. THD + N vs. Frequency, VDD = 2.5 V, RL = 8 Ω + 33 μH, AV = 18 dB
Figure 14. Supply Current vs. Supply Voltage
12
10
8
6
4
2
000.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
07243-015
SHUTDOW N CURRE NT (µ A)
SHUTDOWN VOLTAGE (V)
VDD = 5V
VDD = 2.5V
VDD = 3.6V
Figure 15. Shutdown Current vs. Shutdown Voltage
SSM2305 Data Sheet
Rev. B | Page 8 of 16
3.0
2.5
2.0
1.5
1.0
0.5
0
2.5 3.0
10%
1%
3.5 4.0 4.5 5.0
07243-016
OUTPUT POW ER (W)
SUPPLY VOLT AGE (V)
f = 1kHz
GAI N = 18dB
R
L
= 4Ω + 33µH
Figure 16. Maximum Output Power vs. Supply Voltage,
RL = 4 Ω + 33 μH, AV = 18 dB
3.0
2.5
2.0
1.5
1.0
0.5
0
2.5 3.0 3.5
10%
1%
4.0 4.5 5.0
07243-017
OUTPUT POW ER (W)
SUPPLY VOLT AGE (V)
f = 1kHz
GAI N = 6dB
R
L
= 4Ω + 33µH
Figure 17. Maximum Output Power vs. Supply Voltage,
RL = 4 Ω + 33 μH, AV = 6 dB
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
2.5 3.0 3.5
10%
1%
4.0 4.5 5.0
07243-018
OUTPUT POW ER (W)
SUPPLY VOLT AGE (V)
f = 1kHz
GAI N = 18dB
R
L
= 8Ω + 33µH
Figure 18. Maximum Output Power vs. Supply Voltage,
RL = 8 Ω + 33 μH, AV = 18 dB
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
2.5 3.0 3.5
10%
1%
4.0 4.5 5.0
07243-019
OUTPUT POW ER (W)
SUPPLY VOLT AGE (V)
f = 1kHz
GAI N = 6dB
R
L
= 8Ω + 33µH
Figure 19. Maximum Output Power vs. Supply Voltage,
RL = 8 Ω + 33 μH, AV = 6 dB
Figure 20. Efficiency vs. Output Power into 4 Ω + 33 μH
Figure 21. Efficiency vs. Output Power into 8 Ω + 33 μH
Data Sheet SSM2305
Rev. B | Page 9 of 16
0.6
0.5
0.4
0.3
0.2
0.1
000.5 1.0 1.5 2.0 2.5 3.0
07243-022
POWER DISSIPATI ON (W )
OUTPUT POW ER (W)
VDD = 5.0V
RL = 4Ω + 33µH
Figure 22. Power Dissipation vs. Output Power into 4 Ω + 33 μH
at VDD = 5.0 V
0.20
0.18
0.16
0.14
0.12
0.10
0.08
0.06
0.04
0.02
000.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
07243-023
POWER DISSIPATI ON (W )
OUTPUT POW ER (W)
V
DD
= 5.0V
R
L
= 8Ω + 33µH
Figure 23. Power Dissipation vs. Output Power into 8 Ω + 33 µH
at VDD = 5.0 V
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
07243-024
POWER DISSIPATI ON (W )
OUTPUT POW ER (W)
00.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
VDD = 3.6V
RL = 4Ω + 33µH
Figure 24. Power Dissipation vs. Output Power into 4 Ω + 33 µH
at VDD = 3.6 V
Figure 25. Power Dissipation vs. Output Power into 8 Ω + 33 μH
at VDD = 3.6 V
Figure 26. Supply Current vs. Output Power into 4 Ω + 33 µH
Figure 27. Supply Current vs. Output Power into 8 Ω + 33 μH
SSM2305 Data Sheet
Rev. B | Page 10 of 16
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–10010 100
PSSR (dB)
1000 100000
10000
07243-028
FREQUENCY ( Hz )
Figure 28. Power Supply Rejection Ratio vs. Frequency
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–10010 100
CMRR (dB)
1000 10000010000
07243-029
FREQUENCY ( Hz )
Figure 29. Common-Mode Rejection Ratio vs. Frequency
Figure 30. Turn-On Response
Figure 31. Turn-Off Response
Data Sheet SSM2305
Rev. B | Page 11 of 16
APPLICATIONS INFORMATION
OVERVIEW
The SSM2305 mono Class-D audio amplifier features a filterless
modulation scheme that greatly reduces the external components
count that, in turn, conserves board space, thereby reducing
systems cost. The SSM2305 does not require an output filter,
relying instead on the inherent inductance of the speaker coil
and the natural filtering of the speaker and human ear to fully
recover the audio component of the square wave output. Most
Class-D amplifiers use some variation of pulse-width modulation
(PWM), but the SSM2305 uses Σ-Δ modulation to determine the
switching pattern of the output devices, resulting in a number of
important benefits. Σ-Δ modulators do not produce a sharp peak
with many harmonics in the AM frequency band, as pulse-width
modulators often do. Σ-Δ modulation provides the benefits of
reducing the amplitude of spectral components at high frequencies,
that is, reducing EMI emission that might otherwise be radiated
by speakers and long cable traces. Due to the inherent spread-
spectrum nature of Σ-Δ modulation, the need for oscillator
synchronization is eliminated for designs incorporating multiple
SSM2305 amplifiers.
The SSM2305 also offers protection circuits for overcurrent and
temperature protection.
07243-032
SHUTDOWN
0.1µF
VDD
POP/CLICK
SUPPRESSION
OUT+
OUT–
IN+
VBATT
2.5V TO 5.5V
IN– MODULATOR
(Σ-Δ)
GND
10µF
47nF*
47nF*
*INPUT CAPACIT O RS ARE OPTIONAL IF INPUT DC COMMO N- M ODE
VOLTAGE I S APPROXIMATEL Y V
DD
/2.
EXTERNAL GAIN SETTINGS = 296kΩ/(37kΩ + R
EXT
)
SD
AUDIO IN–
AUDIO IN+
SSM2305
37kΩ
296kΩ
296kΩ
37kΩ
R
EXT
R
EXT
FET
DRIVER
BIAS INTERNAL
OSCILLATOR
Figure 32. Differential Input Configuration, User-Adjustable Gain
07243-033
SHUTDOWN
0.1µF
VDD
POP/CLICK
SUPPRESSION
OUT+
OUT–
MODULATOR
(Σ-Δ)
GND
10µF
SD
SSM2305
37kΩ
296kΩ
296kΩ
37kΩ
REXT
REXT FET
DRIVER
BIAS INTERNAL
OSCILLATOR
EXTERNAL GAIN SETTINGS = 296kΩ/(37kΩ + REXT)
IN+
IN–
AUDIO IN+
VBATT
2.5V TO 5.5V
47nF
47nF
Figure 33. Single-Ended Input Configuration, User-Adjustable Gain
SSM2305 Data Sheet
Rev. B | Page 12 of 16
GAIN
The SSM2305 has a default gain of 18 dB that can be reduced by
using a pair of external resistors with a value calculated as follows:
External Gain Settings = 296 kΩ/(37 kΩ + REXT)
POP-AND-CLICK SUPPRESSION
Voltage transients at the output of audio amplifiers can occur when
shutdown activates or deactivates. Voltage transients as low as
10 mV can be heard as audio pops in the speaker. Clicks and
pops can also be classified as undesirable audible transients gener-
ated by the amplifier system and, therefore, as not coming from
the system input signal. Such transients can be generated when
the amplifier system changes its operating mode. For example, the
following can be sources of audible transients: system power-up/
power-down, mute/unmute, input source change, and sample rate
change. The SSM2305 has a pop-and-click suppression
architecture that reduces these output transients, resulting in
noiseless activation and deactivation.
OUTPUT MODULATION DESCRIPTION
The SSM2305 uses three-level, Σ-Δ output modulation. Each
output is able to swing from GND to VDD, and vice versa. Ideally,
when no input signal is present, the output differential voltage is
0 V because there is no need to generate a pulse. In a real-world
situation, there are always noise sources present. Due to this
constant presence of noise, a differential pulse generates when it
is required in response to this stimulus. A small amount of current
flows into the inductive load when the differential pulse is
generated. However, most of the time output differential voltage is
0 V due to the Analog Devices patented three-level, Σ-Δ output
modulation. This feature ensures that the current flowing through
the inductive load is small.
When the user wants to send an input signal, an output pulse is
generated to follow the input voltage. The differential pulse density
is increased by raising the input signal level. Figure 34 depicts
three-level, Σ-Δ output modulation with and without input stimuli.
07243-003
OUT P UT > 0V +5V
0V
OUT+
+5V
0V
OUT–
+5V
0V
VOUT
OUT P UT < 0V
+5V
0V
OUT+ +5V
0V
OUT–
0V
–5V
VOUT
OUT P UT = 0V
OUT+ +5V
0V
+5V
0V
OUT–
+5V
–5V
0V
VOUT
Figure 34. 3-Level, Σ-Δ Output Modulation with and Without Input Stimuli
LAYOUT
As output power continues to increase, care needs to be taken
to lay out PCB traces and wires properly between the amplifier,
load, and power supply. A good practice is to use short, wide
PCB tracks to decrease voltage drops and minimize inductance.
Ensure that track widths are at least 200 mil for every inch of
track length for lowest dc resistance (DCR), and use 1 oz or 2 oz
of copper PCB traces to further reduce IR drops and inductance.
A poor layout increases voltage drops, consequently affecting
efficiency. Use large traces for the power supply inputs and
amplifier outputs to minimize losses due to parasitic trace
resistance.
Proper grounding guidelines help improve audio performance,
minimize crosstalk between channels, and prevent switching noise
from coupling into the audio signal. To maintain high output swing
and high peak output power, the PCB traces that connect the
output pins to the load and supply pins should be as wide as
possible to maintain the minimum trace resistances. It is also
recommended that a large ground plane be used for minimum
impedances.
In addition, good PCB layouts isolate critical analog paths from
sources of high interference. Separate high frequency circuits
(analog and digital) from low frequency circuits.
Properly designed multilayer PCBs can reduce EMI emission
and increase immunity to the RF field by a factor of 10 or more
compared with double-sided boards. A multilayer board allows
a complete layer to be used for the ground plane, whereas the
ground plane side of a double-sided board is often disrupted with
signal crossover.
If the system has separate analog and digital ground and power
planes, place the analog ground plane underneath the analog
power plane, and, similarly, place the digital ground plane
underneath the digital power plane. There should be no overlap
between analog and digital ground planes or analog and digital
power planes.
INPUT CAPACITOR SELECTION
The SSM2305 does not require input coupling capacitors if the
input signal is biased from 1.0 V to VDD − 1.0 V. Input capacitors
are required if the input signal is not biased within this recom-
mended input dc common-mode voltage range, if high-pass
filtering is needed, or if using a single-ended source. If high-pass
filtering is needed at the input, the input capacitor, together with
the input resistor of the SSM2305, forms a high-pass filter
whose corner frequency is determined by the following
equation:
fC = 1/(2π × RIN × CIN)
The input capacitor can significantly affect the performance of
the circuit. Not using input capacitors degrades both the output
offset of the amplifier and the dc PSRR performance.
Data Sheet SSM2305
Rev. B | Page 13 of 16
PROPER POWER SUPPLY DECOUPLING
To ensure high efficiency, low total harmonic distortion (THD),
and high PSRR, proper power supply decoupling is necessary.
Noise transients on the power supply lines are short duration
voltage spikes. Although the actual switching frequency can range
from 10 kHz to 100 kHz, these spikes can contain frequency
components that extend into the hundreds of megahertz. The
power supply input needs to be decoupled with a good quality
low ESL, low ESR capacitor, usually of around 4.7 µF. This
capacitor bypasses low frequency noises to the ground plane.
For high frequency transient noise, use a 0.1 µF capacitor as
close as possible to the VDD pin of the device. Placing the
decoupling capacitor as close as possible to the SSM2305 helps
maintain efficient performance.
SSM2305 Data Sheet
Rev. B | Page 14 of 16
OUTLINE DIMENSIONS
TOP VIEW
8
1
5
4
0.30
0.25
0.20
BOTTOM VIEW
PIN 1 INDEX
AREA
SEATING
PLANE
0.80
0.75
0.70
1.55
1.45
1.35
1.84
1.74
1.64
0.203 REF
0.05 MAX
0.02 NOM
0.50 BSC
EXPOSED
PAD
3.10
3.00 SQ
2.90
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
0.50
0.40
0.30
COMPLIANT
TO
JEDEC STANDARDS MO-229-WEED
12-07-2010-A
PIN 1
INDICATOR
(R0.15)
Figure 35. 8-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height
(CP-8-13)
Dimensions shown in millimeters
COMPLIANT TO JEDEC STANDARDS MO-187-AA
0.80
0.60
0.40
8°
0°
4
8
1
5
PIN 1 0.65 BSC
SEATING
PLANE
0.38
0.22
1.10 MAX
3.20
3.00
2.80
COPLANARITY
0.10
0.23
0.08
3.20
3.00
2.80
5.15
4.90
4.65
0.15
0.00
0.95
0.85
0.75
Figure 36. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option Branding
SSM2305CPZ-R2 −40°C to +85°C 8-Lead Lead Frame Chip Scale Package [LFCSP] CP-8-13 Y10
SSM2305CPZ-REEL −40°C to +85°C 8-Lead Lead Frame Chip Scale Package [LFCSP] CP-8-13 Y10
SSM2305CPZ-REEL7 −40°C to +85°C 8-Lead Lead Frame Chip Scale Package [LFCSP] CP-8-13 Y10
SSM2305RMZ-R2 −40°C to +85°C 8-Lead Mini Small Outline Package [MSOP] RM-8 Y10
SSM2305RMZ-REEL −40°C to +85°C 8-Lead Mini Small Outline Package [MSOP] RM-8 Y10
SSM2305RMZ-REEL7 −40°C to +85°C 8-Lead Mini Small Outline Package [MSOP] RM-8 Y10
SSM2305-EVALZ
Evaluation Board with LFCSP Model
1 Z = RoHS Compliant Part.
Data Sheet SSM2305
Rev. B | Page 15 of 16
NOTES
SSM2305 Data Sheet
Rev. B | Page 16 of 16
NOTES
©2008–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07243-0-5/16(B)