XS1-L8A-128-QF124 Datasheet
2015/04/14 Document Number: X5358,
XMOS © 2015, All Rights Reserved
XS1-L8A-128-QF124 Datasheet 1
Table of Contents
1 xCORE Multicore Microcontrollers .............................. 2
2 XS1-L8A-128-QF124 Features ................................ 4
3 Pin Configuration ....................................... 5
4 Signal Description ....................................... 6
5 Product Overview ....................................... 10
6 PLL ................................................ 13
7 Boot Procedure ......................................... 14
8 Memory ............................................. 16
9 JTAG ............................................... 17
10 Board Integration ....................................... 19
11 DC and Switching Characteristics .............................. 24
12 Package Information ..................................... 28
13 Ordering Information ..................................... 29
Appendices .............................................. 30
A Configuration of the XS1 ................................... 30
B Processor Status Configuration ............................... 32
C Tile Configuration ....................................... 41
D Node Configuration ...................................... 47
E XMOS USB Interface ...................................... 54
F Device Errata .......................................... 54
G JTAG, xSCOPE and Debugging ................................ 55
H Schematics Design Check List ................................ 57
I PCB Layout Design Check List ................................ 60
J Associated Design Documentation ............................. 61
K Related Documentation .................................... 61
L Revision History ........................................ 62
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X5358, XS1-L8A-128-QF124
XS1-L8A-128-QF124 Datasheet 2
1 xCORE Multicore Microcontrollers
The XS1-L Series is a comprehensive range of 32-bit multicore microcontrollers
that brings the low latency and timing determinism of the xCORE architecture to
mainstream embedded applications. Unlike conventional microcontrollers, xCORE
multicore microcontrollers execute multiple real-time tasks simultaneously and
communicate between tasks using a high speed network. Because xCORE multicore
microcontrollers are completely deterministic, you can write software to implement
functions that traditionally require dedicated hardware.
SRAM
64KB
Security
OTP ROM
JTAG
debug
I/O Pins
Hardware
response
ports
xCORE logical core
xCORE logical core
xCORE logical core
xCORE logical core
xCORE logical core
xCORE logical core
xCORE logical core
xCORE logical core
xTIME: schedulers
timers, clocks
xCONNECT
channels, links
PLL
PLL SRAM
64KB
Security
OTP ROM
JTAG
debug
I/O Pins
Hardware
response
ports
xCORE logical core
xCORE logical core
xCORE logical core
xCORE logical core
xCORE logical core
xCORE logical core
xCORE logical core
xCORE logical core
xTIME: schedulers
timers, clocks
xCONNECT
channels, links
Figure 1:
XS1-L Series:
4-16 core
devices
Key features of the XS1-L8A-128-QF124 include:
·Tiles
: Devices consist of one or more xCORE tiles. Each tile contains between
four and eight 32-bit xCOREs with highly integrated I/O and on-chip memory.
·Logical cores
Each logical core can execute tasks such as computational code,
DSP code, control software (including logic decisions and executing a state
machine) or software that handles I/O. Section 5.1
·xTIME scheduler
The xTIME scheduler performs functions similar to an RTOS,
in hardware. It services and synchronizes events in a core, so there is no
requirement for interrupt handler routines. The xTIME scheduler triggers cores
on events generated by hardware resources such as the I/O pins, communication
channels and timers. Once triggered, a core runs independently and concurrently
to other cores, until it pauses to wait for more events. Section 5.2
X5358, XS1-L8A-128-QF124
XS1-L8A-128-QF124 Datasheet 3
·Channels and channel ends
Tasks running on logical cores communicate using
channels formed between two channel ends. Data can be passed synchronously
or asynchronously between the channel ends assigned to the communicating
tasks. Section 5.5
·xCONNECT Switch and Links
Between tiles, channel communications are im-
plemented over a high performance network of xCONNECT Links and routed
through a hardware xCONNECT Switch. Section 5.6
·Ports
The I/O pins are connected to the processing cores by Hardware Response
ports. The port logic can drive its pins high and low, or it can sample the value
on its pins optionally waiting for a particular condition. Section 5.3
·Clock blocks
xCORE devices include a set of programmable clock blocks that
can be used to govern the rate at which ports execute. Section 5.4
·Memory
Each xCORE Tile integrates a bank of SRAM for instructions and data,
and a block of one-time programmable (OTP) memory that can be configured for
system wide security features. Section 8
·PLL
The PLL is used to create a high-speed processor clock given a low speed
external oscillator. Section 6
·JTAG
The JTAG module can be used for loading programs, boundary scan testing,
in-circuit source-level debugging and programming the OTP memory. Section 9
1.1 Software
Devices are programmed using C, C++ or xC (C with multicore extensions). XMOS
provides tested and proven software libraries, which allow you to quickly add
interface and processor functionality such as USB, Ethernet, PWM, graphics driver,
and audio EQ to your applications.
1.2 xTIMEcomposer Studio
The xTIMEcomposer Studio development environment provides all the tools you
need to write and debug your programs, profile your application, and write images
into flash memory or OTP memory on the device. Because xCORE devices oper-
ate deterministically, they can be simulated like hardware within xTIMEcomposer:
uniquely in the embedded world, xTIMEcomposer Studio therefore includes a static
timing analyzer, cycle-accurate simulator, and high-speed in-circuit instrumenta-
tion.
xTIMEcomposer can be driven from either a graphical development environment,
or the command line. The tools are supported on Windows, Linux and MacOS X
and available at no cost from xmos.com/downloads. Information on using the
tools is provided in the xTIMEcomposer User Guide, X3766.
X5358, XS1-L8A-128-QF124
XS1-L8A-128-QF124 Datasheet 4
2 XS1-L8A-128-QF124 Features
·Multicore Microcontroller with Advanced Multi-Core RISC Architecture
Eight real-time logical cores on 2 xCORE tiles
Cores share up to 500 MIPS
Each logical core has:
Guaranteed throughput of 1
/4of tile MIPS
16x32bit dedicated registers
159 high-density 16/32-bit instructions
All have single clock-cycle execution (except for divide)
32x32
64-bit MAC instructions for DSP, arithmetic and user-definable cryptographic
functions
·Programmable I/O
28 general-purpose I/O pins, configurable as input or output
Up to 32 x 1bit port, 12 x 4bit port, 7 x 8bit port, 3 x 16bit port
4 xCONNECT links
Port sampling rates of up to 60 MHz with respect to an external clock
64 channel ends for communication with other cores, on or off-chip
·Memory
128KB internal single-cycle SRAM (max 64KB per tile) for code and data storage
8KB internal OTP (max 8KB per tile) for application boot code
·Hardware resources
12 clock blocks (6 per tile)
20 timers (10 per tile)
8 locks (4 per tile)
·JTAG Module for On-Chip Debug
·Security Features
Programming lock disables debug and prevents read-back of memory contents
AES bootloader ensures secrecy of IP held on external flash memory
·Ambient Temperature Range
Commercial qualification: 0 °C to 70 °C
Industrial qualification: -40 °C to 85 °C
·Speed Grade
10: 1000 MIPS
8: 800 MIPS
·Power Consumption
Active Mode
400 mA at 500 MHz (typical)
320 mA at 400 MHz (typical)
Standby Mode
28 mA
·124-pin QF124 package 0.5 mm pitch
X5358, XS1-L8A-128-QF124
XS1-L8A-128-QF124 Datasheet 5
3 Pin Configuration
GND
A1
GND
A2
VDDIO
A3
X0D35
A4
X0D34
A5
X0D02
A6
X0D03
A7
X0D04
A8
X0D05
A9
X0D06
A10
X0D07
A11
X0D08
A12
X0D09
A13
X0D10
A14
X0D11
A15
X0D00
A16
X0D01
A17
VDDIO
A18
GND
B1
VDDIO
B2
PCU_
WAKE
B3
PCU_
GATE
B4
PCU_
VDDIO
B5
PCU_
VDD
B6
PCU_
CLK
B7
CLK
B8
RST_N
B9
TDO
B10
TCK
B11
TMS
B12
TDI
B13
TRST_
N
B14
VDDIO
A52
GND
A51
VDDIO
A50
X1D11
A49
X1D10
A48
X1D09
A47
X1D08
A46
X1D07
A45
X1D06
A44
X1D05
A43
X1D04
A42
X1D03
A41
X1D02
A40
X1D01
A39
X1D00
A38
PLL_
AVDD
A37
PLL_
AGND
A36
VDDIO
A35
MODE[4]
B42
VDDIO
B41
X0D29
B40
X0D28
B39
X0D27
B38
X0D26
B37
DEBUG_
N
B36
MODE[3]
B35
MODE[2]
B34
MODE[1]
B33
MODE[0]
B32
OTP_
VCC
B31
X1D39
B30
X1D38
B29
VDDIO
A19
VDD
A20
X1D24
A21
X1D12
A22
X1D22
A23
X1D13
A24
X1D14
A25
X1D15
A26
X1D16
A27
X1D17
A28
X1D23
A29
X1D18
A30
X1D19
A31
X1D20
A32
X1D21
A33
X1D25
A34
VDD
B15
VDD
B16
X1D26
B17
X1D27
B18
X1D28
B19
X1D29
B20
X1D30
B21
X1D31
B22
X1D32
B23
X1D33
B24
X1D34
B25
X1D35
B26
X1D36
B27
X1D37
B28
VDD
A68
VDD
A67
X0D25
A66
X0D21
A65
X0D20
A64
X0D19
A63
X0D18
A62
X0D23
A61
X0D17
A60
X0D16
A59
X0D15
A58
X0D14
A57
X0D13
A56
X0D22
A55
X0D12
A54
X0D24
A53
VDD
B56
VDD
B55
X0D43
B54
X0D42
B53
X0D41
B52
X0D40
B51
X0D39
B50
X0D38
B49
X0D37
B48
X0D36
B47
X0D33
B46
X0D32
B45
X0D31
B44
X0D30
B43
VDD
X5358, XS1-L8A-128-QF124