Rev. 1.91, May. 2017 M393A1K43BB0 M393A1K43BB1 M393A2K40BB0 M393A2K40BB1 M393A2K40BB2 M393A4K40BB0 M393A4K40BB1 M393A4K40BB2 288pin Registered DIMM based on 8Gb B-die 78FBGA with Lead-Free & Halogen-Free (RoHS compliant) datasheet SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND SPECIFICATIONS WITHOUT NOTICE. Products and specifications discussed herein are for reference purposes only. All information discussed herein is provided on an "AS IS" basis, without warranties of any kind. This document and all information discussed herein remain the sole and exclusive property of Samsung Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or otherwise. 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All rights reserved. -1- Registered DIMM Rev. 1.91 datasheet DDR4 SDRAM Revision History Revision No. History Draft Date Remark Editor 1.0 - First SPEC Release Nov. 2014 - J.Y.Lee 1.1 - Change of Part Number (Speed bin "RC") Jan. 2015 - J.Y.Lee 1.2 - Addition of VDDSPD tolerance on page 8 Mar. 2015 - J.Y.Lee 1.3 - Addition of IDD value (M393A2K40BB0-CPB, M393A2K40BB1-CRC, M393A4K40BB1-CRC) on page 25 Apr. 2015 - J.Y.Lee 1.4 - Change of IDD 16th Dec. 2015 - J.Y.Lee 1.5 - Addition of Module line up (8GB) 3rd Feb. 2016 - J.Y.Lee 7th Apr. 2016 - J.Y.Lee 20th Sep. 2016 - J.Y.Lee 4th Oct. 2016 - J.Y.Lee - Change of Physical Dimensions (Module Thickness) 1.6 - Addition of DDR4-2666 1.7 - Addition of IDD value on page 26~27 (M393A1K43BB1-CTD, M393A2K40BB2-CTD, M393A4K40BB2-CTD) 1.8 - Change of Physical Dimensions (32GB) on page 45~47 1.81 - Correction of Typo 17th Mar. 2017 - J.Y.Lee 1.9 - Change Physical dimension. 12th May, 2017 Final J.Y.Bae 19th May, 2017 Final J.Y.Bae 1. Add hole for M393A4K40BB1 and M393A4K40BB2. 2. Remove RCD and SPD of back side dimension for M393A4K40BB0. 1.91 - Add revision history for 1.5version. "Change of Physical Dimensions (Module Thickness)" -2- Registered DIMM datasheet Rev. 1.91 DDR4 SDRAM Table Of Contents 288pin Registered DIMM based on 8Gb B-die 1. DDR4 Registered DIMM Ordering Information ............................................................................................................. 4 2. Key Features................................................................................................................................................................. 4 3. Address Configuration .................................................................................................................................................. 4 4. Registered DIMM Pin Configurations (Front side/Back side)........................................................................................ 5 5. Pin Description ............................................................................................................................................................. 6 6. ON DIMM Thermal Sensor ........................................................................................................................................... 6 7. Input/Output Functional Description.............................................................................................................................. 7 8. Registering Clock Driver Specification .......................................................................................................................... 9 8.1 Timing & Capacitance Values ................................................................................................................................. 9 8.2 Clock Driver Characteristics .................................................................................................................................... 9 9. Function Block Diagram: ............................................................................................................................................... 10 9.1 8GB, 1Gx72 Module (Populated as 1 rank of x8 DDR4 SDRAMs) ......................................................................... 10 9.2 16GB, 2Gx72 Module (Populated as 1 rank of x4 DDR4 SDRAMs) ....................................................................... 11 9.3 32GB, 4Gx72 Module (Populated as 2 ranks of x4 DDR4 SDRAMs) ..................................................................... 12 10. Absolute Maximum Ratings ........................................................................................................................................ 14 10.1 Absolute Maximum DC Ratings............................................................................................................................. 14 11. AC & DC Operating Conditions................................................................................................................................... 14 11.1 Recommended DC Operating Conditions ............................................................................................................. 14 12. AC & DC Input Measurement Levels .......................................................................................................................... 15 12.1 AC & DC Logic Input Levels for Single-Ended Signals ......................................................................................... 15 12.2 AC and DC Input Measurement Levels : VREF Tolerances.................................................................................. 15 12.3 AC and DC Logic Input Levels for Differential Signals .......................................................................................... 16 12.3.1. Differential Signals Definition ......................................................................................................................... 16 12.3.2. Differential Swing Requirements for Clock (CK_t - CK_c) ............................................................................. 16 12.3.3. Single-ended Requirements for Differential Signals ...................................................................................... 17 12.4 Slew Rate Definitions ............................................................................................................................................ 18 12.4.1. Slew Rate Definitions for Differential Input Signals ( CK ) ............................................................................. 18 12.5 Differential Input Cross Point Voltage.................................................................................................................... 19 12.6 Single-ended AC & DC Output Levels................................................................................................................... 20 12.7 Differential AC & DC Output Levels....................................................................................................................... 20 12.8 Single-ended Output Slew Rate ............................................................................................................................ 20 12.9 Differential Output Slew Rate ................................................................................................................................ 21 12.10 Single-ended AC & DC Output Levels of Connectivity Test Mode ...................................................................... 22 12.11 Test Load for Connectivity Test Mode Timing ..................................................................................................... 22 13. DIMM IDD Specification Definition .............................................................................................................................. 23 14. IDD SPEC Table ......................................................................................................................................................... 26 15. Input/Output Capacitance ........................................................................................................................................... 30 16. Electrical Characterisitics and AC Timing ................................................................................................................... 31 16.1 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin ................................................................ 31 16.2 Speed Bin Table Note ........................................................................................................................................... 36 17. Timing Parameters by Speed Grade .......................................................................................................................... 37 18. Physical Dimensions................................................................................................................................................... 43 18.1 1Gx8 based 1Gx72 Module (1 Rank) - M393A1K43BB0 ...................................................................................... 43 18.1.1. x72 DIMM, populated as one physical rank of x8 DDR4 SDRAMs................................................................ 43 18.2 1Gx8 based 1Gx72 Module (1 Rank) - M393A1K43BB1 ...................................................................................... 44 18.2.1. x72 DIMM, populated as one physical rank of x8 DDR4 SDRAMs................................................................ 44 18.3 2Gx4 based 2Gx72 Module (1 Rank) - M393A2K40BB0/M393A2K40BB1/M393A2K40BB2 ............................... 45 18.3.1. 2Gx72 DIMM, populated as one physical rank of x4 DDR4 SDRAMs ........................................................... 45 18.4 2Gx4 based 4Gx72 Module (2 Ranks) - M393A4K40BB0 .................................................................................... 46 18.4.1. 4Gx72 DIMM, populated as two physical ranks of x4 DDR4 SDRAMs.......................................................... 46 18.5 2Gx4 based 4Gx72 Module (2 Ranks) - M393A4K40BB1 .................................................................................... 47 18.5.1. 4Gx72 DIMM, populated as two physical ranks of x4 DDR4 SDRAMs.......................................................... 47 18.6 2Gx4 based 4Gx72 Module (2 Ranks) - M393A4K40BB2 .................................................................................... 48 18.6.1. 4Gx72 DIMM, populated as two physical ranks of x4 DDR4 SDRAMs.......................................................... 48 -3- Rev. 1.91 datasheet Registered DIMM DDR4 SDRAM 1. DDR4 Registered DIMM Ordering Information Part Number2 Density Organization Component Composition1 Number of Rank Height M393A1K43BB0-CPB/RC M393A1K43BB1-CTD 8GB 1Gx72 1Gx8(K4A8G085WB-BC##)*9 1 31.25mm M393A2K40BB0-CPB M393A2K40BB1-CRC M393A2K40BB2-CTD 16GB 2Gx72 2Gx4(K4A8G045WB-BC##)*18 1 31.25mm M393A4K40BB0-CPB M393A4K40BB1-CRC M393A4K40BB2-CTD 32GB 4Gx72 2Gx4(K4A8G045WB-BC##)*36 2 31.25mm NOTE : 1. "##" - PB/RC/TD 2. PB(2133Mbps 15-15-15)/RC(2400Mbps 17-17-17)/TD(2666Mbps 19-19-19) - DDR4-2666(19-19-19) is backward compatible to DDR4-2400(17-17-17) 2. Key Features Speed DDR4-1600 DDR4-1866 DDR4-2133 DDR4-2400 DDR4-2666 11-11-11 13-13-13 15-15-15 17-17-17 19-19-19 Unit tCK(min) 1.25 1.071 0.937 0.833 0.75 ns CAS Latency 11 13 15 17 19 nCK tRCD(min) 13.75 13.92 14.06 14.16 14.25 ns tRP(min) 13.75 13.92 14.06 14.16 14.25 ns tRAS(min) 35 34 33 32 32 ns tRC(min) 48.75 47.92 47.06 46.16 46.25 ns * JEDEC standard 1.2V 0.06V Power Supply * VDDQ = 1.2V 0.06V * 800 MHz fCK for 1600Mb/sec/pin,933 MHz fCK for 1866Mb/sec/pin, 1067MHz fCK for 2133Mb/sec/pin,1200MHz fCK for 2400Mb/sec/pin, 1333MHz fCK for 2666Mb/sec/pin * 16 Banks (4 Bank Groups) * Programmable CAS Latency: 10,11,12,13,14,15,16,17,18,19,20 * Programmable Additive Latency (Posted CAS): 0, CL - 2, or CL - 1 clock * Programmable CAS Write Latency (CWL) = 9,11 (DDR4-1600), 10,12 (DDR4-1866), 11,14 (DDR4-2133), 12,16 (DDR4-2400) and 14,18 (DDR42666) * Burst Length: 8, 4 with tCCD = 4 which does not allow seamless read or write [either On the fly using A12 or MRS] * Bi-directional Differential Data Strobe * On Die Termination using ODT pin * Average Refresh Period 7.8us at lower then TCASE 85C, 3.9us at 85C < TCASE 95C * Asynchronous Reset 3. Address Configuration Organization Row Address Column Address Bank Group Address Bank Address Auto Precharge 2Gx4(8Gb) based Module A0-A16 A0-A9 BG0-BG1 BA0-BA1 A10/AP -4- Rev. 1.91 datasheet Registered DIMM DDR4 SDRAM 4. Registered DIMM Pin Configurations (Front side/Back side) Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back Pin Front Pin 1 12V3,NC 145 12V3,NC 40 184 VSS 78 EVENT_n 222 PARITY 117 DQ52 261 VSS 2 VSS 146 VREFCA 41 TDQS12_t, DQS12_t TDQS12_c, DQS12_c Back 185 DQS3_c 79 A0 223 VDD 118 VSS 262 DQ53 3 DQ4 147 VSS 42 VSS 186 DQS3_t 80 VDD 224 BA1 119 DQ48 263 VSS 4 VSS 148 DQ5 43 DQ30 187 VSS 81 BA0 225 A10/AP 120 VSS 264 DQ49 TDQS15_t, DQS15_t TDQS15_c, DQS15_c 265 VSS 266 DQS6_c DQ0 149 VSS 44 VSS 188 DQ31 82 RAS_n/A16 226 VDD 121 6 VSS 150 DQ1 45 DQ26 189 VSS 83 VDD 227 RFU 122 7 TDQS9_t, DQS9_t TDQS9_c, DQS9_c 151 VSS 46 VSS 190 DQ27 84 S0_n 228 WE_n/A14 123 VSS 267 DQS6_t 152 DQS0_c 47 CB4 191 VSS 85 VDD 229 VDD 124 DQ54 268 VSS 9 VSS 153 DQS0_t 48 VSS 192 CB5 86 CAS_n/A15 230 NC 125 VSS 269 DQ55 10 DQ6 154 VSS 49 CB0 193 VSS 87 ODT0 231 VDD 126 DQ50 270 VSS 5 8 11 VSS 155 DQ7 50 VSS 194 CB1 88 VDD 232 A13 127 VSS 271 DQ51 12 DQ2 156 VSS 51 195 VSS 89 S1_n 233 VDD 128 DQ60 272 VSS 13 VSS 157 DQ3 52 TDQS17_t, DQS17_t TDQS17_c, DQS17_c 196 DQS8_c 90 VDD 234 A17 129 VSS 273 DQ61 14 DQ12 158 VSS 53 VSS 197 DQS8_t 91 ODT1 235 NC,C2 130 DQ56 274 VSS 15 VSS 159 DQ13 54 CB6 198 VSS 92 VDD 236 VDD 131 275 DQ57 276 VSS 277 DQS7_c DQ8 160 VSS 55 VSS 199 CB7 93 C0,CS2_n,NC 17 VSS 161 DQ9 56 CB2 200 VSS 94 VSS 238 SA2 133 18 TDQS10_t, DQS10_t TDQS10_c, DQS10_c 162 VSS 57 VSS 201 CB3 95 DQ36 239 VSS 134 VSS 278 DQS7_t 163 DQS1_c 58 RESET_n 202 VSS 96 VSS 240 DQ37 135 DQ62 279 VSS 20 VSS 164 DQS1_t 59 VDD 203 CKE1 97 DQ32 241 VSS 136 VSS 280 DQ63 21 DQ14 165 VSS 60 CKE0 204 VDD 98 VSS 242 DQ33 137 DQ58 281 VSS TDQS13_t, DQS13_t TDQS13_c, DQS13_c 243 VSS 138 VSS 282 DQ59 244 DQS4_c 139 SA0 283 VSS 16 19 237 NC,CS3_c,C1 132 VSS TDQS16_t, DQS16_t TDQS16_c, DQS16_c 22 VSS 166 DQ15 61 VDD 205 RFU 99 23 DQ10 167 VSS 62 ACT_n 206 VDD 100 24 VSS 168 DQ11 63 BG0 207 BG1 101 VSS 245 DQS4_t 140 SA1 284 VDDSPD 25 DQ20 169 VSS 64 VDD 208 ALERT_n 102 DQ38 246 VSS 141 SCL 285 SDA 26 VSS 170 DQ21 65 A12/BC_n 209 VDD 103 VSS 247 DQ39 142 VPP 286 VPP 27 DQ16 171 VSS 66 A9 210 A11 104 DQ34 248 VSS 143 VPP 287 VPP 28 VSS 172 DQ17 67 VDD 211 A7 105 VSS 249 DQ35 144 RFU 288 VPP4 29 TDQS11_t, DQS11_t TDQS11_c, DQS11_c 173 VSS 68 A8 212 VDD 106 DQ44 250 VSS 174 DQS2_c 69 A6 213 A5 107 VSS 251 DQ45 31 VSS 175 DQS2_t 70 VDD 214 A4 108 DQ40 252 VSS 32 DQ22 176 VSS 71 A3 215 VDD 109 VSS 253 DQ41 TDQS14_t, DQS14_t TDQS14_c, DQS14_c 254 VSS 255 DQS5_c 30 33 VSS 177 DQ23 72 A1 216 A2 110 34 DQ18 178 VSS 73 VDD 217 VDD 111 35 VSS 179 DQ19 74 CK0_t 218 CK1_t 112 VSS 256 DQS5_t 36 DQ28 180 VSS 75 CK0_c 219 CK1_c 113 DQ46 257 VSS 37 VSS 181 DQ29 76 VDD 220 VDD 114 VSS 258 DQ47 38 DQ24 182 VSS 77 VTT 221 VTT 115 DQ42 259 VSS 39 VSS 183 DQ25 116 VSS 260 DQ43 KEY NOTE: 1. VPP is 2.5V DC 2. Pin 230 is defined as NC for UDIMMs, RDIMMs and LRDIMMs. Pin 230 is defined as SAVE_n for NVDIMMs. 3. Pins 1 and 145 are defined as NC for UDIMMs, RDIMMs and LRDIMMs. Pins 1 and 145 are defined as 12V for Hybrid /NVDIMM 4. The 5th VPP is required on all modules. DIMMs. -5- Rev. 1.91 datasheet Registered DIMM DDR4 SDRAM 5. Pin Description Pin Name 1 Description Pin Name Description Register address input SCL I2C serial bus clock for SPD/TS and register BA0, BA1 Register bank select input SDA I2C serial bus data line for SPD/TS and register BG0, BG1 Register bank group select input A0-A17 I2C slave address select for SPD/TS and register SA0-SA2 RAS_n 2 Register row address strobe input PAR Register parity input CAS_n 3 Register column address strobe input VDD SDRAM core power supply 4 Register write enable input VPP SDRAM activating power supply WE_n CS0_n, CS1_n, CS2_n, CS3_n DIMM Rank Select Lines input VREFCA CKE0, CKE1 Register clock enable lines input ODT0, ODT1 Register on-die termination control lines input ACT_n SDRAM command/address reference supply VSS Power supply return (ground) VDDSPD Serial SPD/TS positive power supply Register input for activate input ALERT_n Register ALERT_n output DIMM memory data bus RESET_n Set Register and SDRAMs to a Known State CB0-CB7 DIMM ECC check bits EVENT_n SPD signals a thermal event has occurred DQS0_t- DQS17_t Data Buffer data strobes (positive line of differential pair) VTT SDRAM I/O termination supply DQS0_c- DQS17_c Data Buffer data strobes (negative line of differential pair) RFU Reserved for future use DQ0-DQ63 CK0_t, CK1_t Register clock input (positive line of differential pair) CK0_c, CK1_c Register clocks input (negative line of differential pair) NOTE : 1. Address A17 is only valid for 16 Gb x4 based SDRAMs. 2. RAS_n is a multiplexed function with A16. 3. CAS_n is a multiplexed function with A15. 4. WE_n is a multiplexed function with A14. 6. ON DIMM Thermal Sensor SA2 SA1 SA0 1K SA0 SCL SCL SDA SDA SA1 SA2 EVENT_n Serial PD with Thermal sensor SA0 SA1 SA2 SCL SDA EVENT_n ZQCAL VSS Register NOTE : 1. All Samsung RDIMM support Thermal sensor on DIMM [ Table 1 ] Temperature Sensor Characteristics Grade B Range Temperature Sensor Accuracy Min. Typ. Max. 75 < Ta < 95 - +/- 0.5 +/- 1.0 40 < Ta < 125 - +/- 1.0 +/- 2.0 -20 < Ta < 125 - +/- 2.0 +/- 3.0 Resolution 0.25 -6- Units NOTE - C - C /LSB - Registered DIMM datasheet Rev. 1.91 DDR4 SDRAM 7. Input/Output Functional Description Symbol Type Function CK0_t, CK0_c, CK1_t, CK1_c Input Clock: CK_t and CK_c are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK_t and negative edge of CK_c. CKE0, CKE1 Input Clock Enable: CKE HIGH activates and CKE LOW deactivates internal clock signals and device input buffers and output drivers. Taking CKE LOW provides Precharge Power-Down and Self-Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is synchronous for Self-Refresh exit. After VREFCA and Internal DQ Vref have become stable during the power on and initialization sequence, they must be maintained during all operations (including Self-Refresh). CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK_t, CK_c, ODT and CKE, are disabled during power-down. Input buffers, excluding CKE, are disabled during Self-Refresh. CS0_n, CS1_n, CS2_n, CS3_n Input Chip Select: All commands are masked when CS_n is registered HIGH. CS_n provides for external Rank selection. CS_n is considered part of the command code. C0, C1, C2 Input Chip ID : Chip ID is only used for 3DS for 2,4,8 high stack via TSV to select each slice of stacked component. Chip ID is considered part of the command code. ODT0, ODT1 Input On Die Termination: ODT (registered HIGH) enables RTT_NOM termination resistance internal to the DDR4 SDRAM. When enabled, ODT is only applied to each DQ, DQS_t, DQS_c, TDQS_t and TDQS_c signal. The ODT pin will be ignored if MR1 is programmed to disable RTT_NOM. ACT_n Input Activation Command Input : ACT_n defines the Activation command being entered along with CS_n. The input into RAS_n/A16, CAS_n/A15 and WE_n/A14 will be considered as Row Address A16, A15 and A14 RAS_n/A16. CAS_n/A15. WE_n/A14 Input Command Inputs: RAS_n/A16, CAS_n/A15 and WE_n/A14 (along with CS_n) define the command being entered. Those pins have multi function. For example, for activation with ACT_n Low, these are Addresses like A16, A15 and A14 but for non-activation command with ACT_n High, these are Command pins for Read, Write and other command defined in command truth table BG0 - BG1 Input Bank Group Inputs: BG0 - BG1 define which bank group an Active, Read, Write or Precharge command is being applied. BG0 also determines which mode register is to be accessed during a MRS cycle. BA0 - BA1 Input Bank Address Inputs: BA0 - BA1 define to which bank an Active, Read, Write or Precharge command is being applied. Bank address also determines which mode register is to be accessed during a MRS cycle. A0 - A17 Input Address Inputs: Provide the row address for ACTIVATE Commands and the column address for Read/Write commands to select one location out of the memory array in the respective bank. A10/AP, A12/BC_n, RAS_n/A16, CAS_n/A15 and WE_n/A14 have additional functions. See other rows. The address inputs also provide the op-code during Mode Register Set commands. A17 is only defined for 16 Gb x4 SDRAM configurations. A10 / AP Input Auto-precharge: A10 is sampled during Read/Write commands to determine whether Autoprecharge should be performed to the accessed bank after the Read/Write operation. (HIGH: Autoprecharge; LOW: no Autoprecharge). A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by bank addresses. A12 / BC_n Input Burst Chop: A12/BC_n is sampled during Read and Write commands to determine if burst chop (on-thefly) will be performed. (HIGH, no burst chop; LOW: burst chopped). See command truth table for details. RESET_n CMOS Input Active Low Asynchronous Reset: Reset is active when RESET_n is LOW, and inactive when RESET_n is HIGH. RESET_n must be HIGH during normal operation. DQ Input/ Output Data Input/ Output: Bi-directional data bus. If CRC is enabled via Mode register then CRC code is added at the end of Data Burst. Any DQ from DQ0-DQ3 may indicate the internal Vref level during test via Mode Register Setting MR4 A4=High. Refer to vendor specific data sheets to determine which DQ is used. DQS0_t-DQS17_t, DQS0_c-DQS17_c Input/ Output Data Strobe: output with read data, input with write data. Edge-aligned with read data, centered in write data. The data strobe DQS_t is paired with differential signals DQS_c, respectively, to provide differential pair signaling to the system during reads and writes. DDR4 SDRAM supports differential data strobe only and does not support single-ended. Input Command and Address Parity Input: DDR4 Supports Even Parity check in SDRAMs with MR setting. Once it's enabled via Register in MR5, then SDRAM calculates Parity with ACT_n, RAS_n/A16, CAS_n/A15, WE_n/A14, BG0-BG1, BA0-BA1, A17-A0. Input parity should be maintained at the rising edge of the clock and at the same time with command & address with CS_n LOW Output (Input) Alert : It has multi functions such as CRC error flag, Command and Address Parity error flag as Output signal. If there is error in CRC, then ALERT_n goes LOW for the period time interval and goes back HIGH. If there is error in Command Address Parity Check, then ALERT_n goes LOW for relatively long period until on going SDRAM internal recovery transaction is complete. During Connectivity Test mode this pin functions as an input. Using this signal or not is dependent on the system. If the SDRAM ALERT_n pins are not connected to the ALERT_n pin on the edge connector is must still be connected to VDD on DIMM. PAR ALERT_n RFU NC Reserved for Future Use: No on DIMM electrical connection is present No Connect: No on DIMM electrical connection is present -7- datasheet Registered DIMM Symbol Type Rev. 1.91 DDR4 SDRAM Function VDD1 Supply Power Supply: 1.2 V 0.06 V VSS Supply Ground VTT Supply VDD/2 VPP Supply SDRAM Activating Power Supply: 2.5V ( 2.375V min, 2.75V max) VDDSPD Supply SPD and register supply voltage. Register requires the nominl volatge to be 2.5V 10%. VREFCA Supply Reference voltage for CA NOTE : 1. For PC4 VDD is 1.2V. For PC4L VDD is TBD. -8- Rev. 1.91 datasheet Registered DIMM DDR4 SDRAM 8. Registering Clock Driver Specification 8.1 Timing & Capacitance Values Symbol Parameter DDR4-1600/1866/2133 Conditions Max Min Max Units fclock Input Clock Frequency 625 1080 625 1350 MHz tCH/tCL Pulse duration, CK_t, CK_c HIGH or LOW 0.4 - 0.4 - tCK tACT Inputs active time4 before DRST_n is DCKE0/1 = LOW and DCS0/ taken HIGH 1_n = HIGH 16 - 16 - tCK tPDM Propagation delay, single-bit switching, CK_t/ CK_c to output 1.2V Operation 1 1.3 1 1.3 ns tDIS output disable time Rising edge of Yn_t to output float 0.5*tCK + tQSK1(min) - 0.5*tCK + tQSK1(min) - ps tEN output enable time Output valid to rising edge of 0.5*tCK Yn_t tQSK1(max) - 0.5*tCK tQSK1(max) - ps CI Input capacitance, Data inputs NOTE1,2 0.8 1.1 0.8 1.0 Input capacitance, CK_t, CK_c NOTE1,2 0.8 1.1 0.8 1.0 Input capacitance, DRST_n VI=VDD or VSS ; VDD=1.2V 0.5 2.0 0.5 2.0 CCK CIR application frequency DDR4-2400/2666 Min Notes pF Note: 1. This parameter does not include package capacitance 2. Data inputs are DCKE0/1, DODT0/1, DA0..DA17, DBA0..DBA1, DBG0..DBG1, DACT_n, DC0..DC2, DPAR, DCS0/1_n 8.2 Clock Driver Characteristics Symbol Parameter tjit (cc) Cycle-to-cycle period jitter tSTAB Stabilization time tCKsk Clock Output skew Conditions CK_t/CK_c stable DDR4-1600/1866/ 2133 DDR4-2400 DDR4-2666 Units Min Max Min Max Min Max 0 0.025 x tCK 0 0.025 x tCK 0 0.025 x tCK ps - 5 - 5 - 5 us - 10 - 10 - 10 ps 0.025 * tCK -0.025 * tCK 0.025 * tCK -0.025 * tCK 0.025 * tCK ps -0.032 * tCK 0.032 * tCK ps tjit(per) Yn Clock Period jitter -0.025 * tCK tjit(hper) Half period jitter -0.032 * tCK 0.032 * tCK -0.032 * tCK 0.032 * tCK tQsk1 Qn Output to clock tolerance -0.125 * tCK 0.125 * tCK -0.125 * tCK 0.125 * tCK tdynoff Maximum re-driven dynamic clock off-set - 50 - 45 -9- -0.1 * tCK 0.1 * tCK - 45 ps ps Notes Rev. 1.91 datasheet Registered DIMM DDR4 SDRAM 9. Function Block Diagram: 9.1 8GB, 1Gx72 Module (Populated as 1 rank of x8 DDR4 SDRAMs) DBI7_n/DM7_n DQS7_t DQS7_c DQ[63:56] VSS VSS ZQ DBI_n/DM_n DQS_t D7 DQS_c DQ[7:0] CKE ODT CS_n VSS CKE ODT CS_n D6 DBI_n/DM_n DQS_t D8 DQS_c DQ[7:0] ZQ ZQ DBI_n/DM_n D4 DQS_t DQS_c DQ[3:0] DBI8_n/DM8_n DQS8_t DQS8_c CB[7:0] DBI6_n/DM6_n DQS6_t DQS6_c DQ[55:48] ZQ DBI_n/DM_n DQS_t D3 DQS_c DQ[7:0] CKE ODT CS_n DBI3_n/DM3_n DQS3_t DQS3_c DQ[31:24] DBI_n/DM_n DQS_t DQS_c DQ[3:0] CKE ODT CS_n VSS CKE ODT CS_n ZQ DBI_n/DM_n DQS_t D2 DQS_c DQ[7:0] DBI2_n/DM2_n DQS2_t DQS2_c DQ[23:16] DBI5_n/DM5_n DQS5_t DQS5_c DQ[47:40] D1 ZQ VSS DBI_n/DM_n DQS_t DQS_c DQ[7:0] DBI_n/DM_n DQS_t D5 DQS_c DQ[7:0] CKE ODT CS_n VSS ZQ VSS DBI1_n/DM1_n DQS1_t DQS1_c DQ[15:8] DBI4_n/DM4_n DQS4_t DQS4_c DQ[39:32] ZQ VSS VSS ZQ DBI_n/DM_n DQS_t D0 DQS_c DQ[7:0] CKE ODT CS_n DBI0_n/DM0_n DQS0_t DQS0_c DQ[7:0] CKE ODT CS_n CS0B_n ODT0B CKE0B CKE ODT CS_n CS0A_n ODT0A CKE0A VDDSPD Serial PD VPP D0 - D8 VDD D0 - D8 BG[1:0] BG[1:0]A -> BG[1:0] : SDRAMs D[4:0] BG[1:0]B -> BG[1:0] : SDRAMs D[8:5] BA[1:0] BA1:0]A -> BA[1:0] : SDRAMs D[4:0] BA[1:0]B -> BA[1:0] : SDRAMs D[8:5] A[16:0] A[16:0]A -> A[16:0] : SDRAMs D[4:0] A[16:0]B -> A[16:0] : SDRAMs D[8:5] PARITY, ACT_n CKE0 ODT0 VTT CS0_n VREFCA D0 - D8 VSS D0 - D8 PARA -> PAR, ACT_n : SDRAMs D[4:0] PARB -> PAR, ACT_n : SDRAMs D[8:5] R E G I S T E R CKE0A -> CKE : SDRAMs D[4:0] CKE0B -> CKE : SDRAMs D[8:5] ODT0A -> ODT : SDRAMs D[4:0] ODT0B -> ODT : SDRAMs D[8:5] CS0A_n -> CS_n : SDRAMs D[4:0] CS0B_n -> CS_n : SDRAMs D[8:5] CK0_t Y0(_t, _c) -> CK0(_t, _c) : SDRAMs D[8:5] SA1 CK0_c Y1(_t, _c) -> CK1(_t, _c) : SDRAMs D[4:0] SA0 CK1_t SA2 1K SA0 SCL SCL SDA SDA SA1 SA2 EVENT_n Serial PD with Thermal sensor SA0 SA1 CK1_c SA2 RESET_n SCL SDA EVENT_n ZQCAL VSS Register NOTE : 1. Unless otherwise noted, resistor values are 15 5%. 2. See the Net Structure diagrams for all resistors associated with the command, address and control bus. 3. ZQ resistors are 240 1% . For all other resistor values refer to the appropriate wiring diagram. - 10 - QRESET_n : All SDRAMs Rev. 1.91 datasheet Registered DIMM DDR4 SDRAM 9.2 16GB, 2Gx72 Module (Populated as 1 rank of x4 DDR4 SDRAMs) DQS_t DQS_c DQ[3:0] D10 DQS17_t DQS17_c CB[7:4] VDDSPD Serial PD VPP D1 - D18 VDD D1 - D18 D1 - D18 VSS D1 - D18 CKE ODT CS_n VSS VSS VSS CKE ODT CS_n CKE ODT CS_n ZQ DQS_t DQS_c DQ[3:0] ACT_n QAACT_n -> ACT_n : SDRAMs D[10:1] QBACT_n -> ACT_n : SDRAMs D[18:11] PARITY QAPAR -> PAR : SDRAMs D[10:1] QBPAR -> PAR : SDRAMs D[18:11] QACKE0 -> CKE : SDRAMs D[10:1] QBCKE0 -> CKE : SDRAMs D[18:11] CKE0 ODT0 VTT VREFCA DQS_t DQS_c DQ[3:0] QABG[1:0] -> BG[1:0] : SDRAMs D[10:1] QBBG[1:0] -> BG[1:0] : SDRAMs D[18:11] QABA[1:0] -> BA[1:0] : SDRAMs D[10:1] QBBA[1:0] -> BA[1:0] : SDRAMs D[18:11] QAA[17:0] -> A[17:0] : SDRAMs D[10:1] QBA[17:0] -> A[17:0] : SDRAMs D[18:11] A[17:0] DQS_t DQS_c DQ[3:0] ZQ D18 DQS16_t DQS16_c DQ[63:60] BA[1:0] VSS DQS8_t DQS8_c CB[3:0] CKE ODT CS_n VSS CKE ODT CS_n D5 ZQ CKE ODT CS_n VSS VSS VSS ZQ BG[1:0] ZQ DQS_t DQS_c DQ[3:0] CS0_n R E G I S T E R QAODT0 -> ODT : SDRAMs D[10:1] QBODT0 -> ODT : SDRAMs D[18:11] QACS0_n -> CS_n : SDRAMs D[10:1] QBCS0_n -> CS_n : SDRAMs D[18:11] SA2 SA1 SA0 CK0_t Y0_t -> CK_t : SDRAMs D[18:11] Y1_t -> CK_t : SDRAMs D[10:1] CK0_c Y0_c -> CK_c : SDRAMs D[18:11] Y1_c -> CK_c : SDRAMs D[10:1] 1K SA0 SCL SCL SDA SDA SA1 SA0 SA2 EVENT_n Serial PD with Thermal sensor SA1 SA2 SCL CK1_t CK1_c SDA EVENT_n ZQCAL VSS Register RESET_n QRST_n -> RESET_n : All SDRAMs ALERT_n ERROR_IN_n -> ALERT_n : All SDRAMs NOTE : 1. Unless otherwise noted, resistor values are 15 5%. 2. See the Net Structure diagrams for all resistors associated with the command, address and control bus. 3. ZQ resistors are 240 1% . For all other resistor values refer to the appropriate wiring diagram. - 11 - VSS CKE ODT CS_n VSS CKE ODT CS_n VSS CKE ODT CS_n DQS_t DQS_c DQ[3:0] ZQ D17 DQS15_t DQS15_c DQ[55:52] D14 DQS7_t DQS7_c DQ[59:56] DQS_t DQS_c DQ[3:0] ZQ DQS_t DQS_c DQ[3:0] DQS_t DQS_c DQ[3:0] D16 DQS14_t DQS14_c DQ[47:44] CKE ODT CS_n CKE ODT CS_n VSS CKE ODT CS_n ZQ D9 DQS12_t DQS12_c DQ[31:28] ZQ DQS_t DQS_c DQ[3:0] ZQ D15 DQS13_t DQS13_c DQ[39:36] D13 DQS6_t DQS6_c DQ[51:48] DQS_t DQS_c DQ[3:0] ZQ DQS_t DQS_c DQ[3:0] VSS CKE ODT CS_n D8 DQS11_t DQS11_c DQ[23:20] D4 DQS3_t DQS3_c DQ[27:24] ZQ VSS D3 DQS_t DQS_c DQ[3:0] D12 DQS5_t DQS5_c DQ[43:40] CKE ODT CS_n VSS ZQ DQS_t DQS_c DQ[3:0] ZQ DQS_t DQS_c DQ[3:0] ZQ D11 DQS4_t DQS4_c DQ[35:32] D7 DQS10_t DQS10_c DQ[15:12] CKE ODT CS_n DQS_t DQS_c DQ[3:0] DQS2_t DQS2_c DQ[19:16] DQS_t DQS_c DQ[3:0] ZQ D2 DQS1_t DQS1_c DQ[11:8] D6 DQS9_t DQS9_c DQ[7:4] VSS CKE ODT CS_n DQS_t DQS_c DQ[3:0] ZQ VSS VSS ZQ D1 DQS0_t DQS0_c DQ[3:0] CKE ODT CS_n QBCS0_n QBODT0 QBCKE0 CKE ODT CS_n QACS0_n QAODT0 QACKE0 Rev. 1.91 datasheet Registered DIMM DDR4 SDRAM 9.3 32GB, 4Gx72 Module (Populated as 2 ranks of x4 DDR4 SDRAMs) QACS0_n QAODT0 QACKE0 1K SA1 SA2 SA0 SCL SCL SCL SDA SDA SDA EVENT_n Serial PD with Thermal sensor EVENT_n SA1 SA2 DQS_t DQS_c DQ[3:0] VSS Register - 12 - VSS CKE ODT CS_n D12 VSS CKE ODT CS_n ZQ D13 ZQ VSS CKE ODT CS_n DQS_t DQS_c DQ[3:0] D14 DQS_t DQS_c DQ[3:0] D15 DQS_t DQS_c DQ[3:0] VDDSPD Serial PD VPP D1 - D36 VDD D1 - D36 VREFCA D1 - D36 VSS D1 - D36 NOTE : 1. Unless otherwise noted, resistor values are 15 5%. 2. See the Net Structure diagrams for all resistors associated with the command, address and control bus. 3. ZQ resistors are 240 1% . For all other resistor values refer to the appropriate wiring diagram. ZQ DQS_t DQS_c DQ[3:0] VTT ZQCAL VSS CKE ODT CS_n D11 DQS_t DQS_c DQ[3:0] CKE ODT CS_n VSS VSS ZQ ZQ ZQ VSS DQS17_t DQS17_c CB[7:4] SA1 SA0 VSS CKE ODT CS_n CKE ODT CS_n D5 SA2 SA0 DQS_t DQS_c DQ[3:0] ZQ DQS_t DQS_c DQ[3:0] VSS CKE ODT CS_n CKE ODT CS_n VSS D4 DQS12_t DQS12_c DQ[31:28] D20 ZQ VSS VSS DQS_t DQS_c DQ[3:0] VSS CKE ODT CS_n D19 ZQ DQS_t DQS_c DQ[3:0] ZQ DQS_t DQS_c DQ[3:0] ZQ D3 DQS11_t DQS11_c DQ[23:20] CKE ODT CS_n VSS CKE ODT CS_n DQS_t DQS_c DQ[3:0] D10 DQS8_t DQS8_c CB[3:0] D18 ZQ D9 DQS3_t DQS3_c DQ[27:24] ZQ DQS_t DQS_c DQ[3:0] ZQ DQS_t DQS_c DQ[3:0] CKE ODT CS_n CKE ODT CS_n DQS_t DQS_c DQ[3:0] DQS_t DQS_c DQ[3:0] D2 DQS10_t DQS10_c DQ[15:12] CKE ODT CS_n VSS ZQ D8 DQS2_t DQS2_c DQ[19:16] D17 DQS_t DQS_c DQ[3:0] VSS CKE ODT CS_n DQS_t DQS_c DQ[3:0] ZQ D1 DQS9_t DQS9_c DQ[7:4] ZQ CKE ODT CS_n VSS ZQ D7 DQS1_t DQS1_c DQ[11:8] D16 DQS_t DQS_c DQ[3:0] VSS CKE ODT CS_n DQS_t DQS_c DQ[3:0] ZQ VSS VSS ZQ D6 DQS0_t DQS0_c DQ[3:0] CKE ODT CS_n CKE ODT CS_n QACS1_n QAODT1 QACKE1 Rev. 1.91 datasheet Registered DIMM DDR4 SDRAM QBCS0_n QBODT0 QBCKE0 BG[1:0] A[17:0] D36 QAACT_n -> ACT_n : SDRAMs D[20:1] QBACT_n -> ACT_n : SDRAMs D[36:21] C[2:0] QAC[2:0] -> C[2:0] : SDRAMs D[20:1] QBC[2:0] -> C[2:0] : SDRAMs D[36:21] PARITY QAPAR -> PAR : SDRAMs D[20:1] QBPAR -> PAR : SDRAMs D[36:21] QACKE0 -> CKE : SDRAMs D[10:1] QBCKE0 -> CKE : SDRAMs D[28:21] ODT0 ODT1 CS0_n CS1_n CK0_t CK0_c CK1_t CK1_c RESET_n ALERT_n D24 DQS16_t DQS16_c DQ[63:60] DQS_t DQS_c DQ[3:0] VSS CKE ODT CS_n ZQ VSS CKE ODT CS_n D30 ZQ VSS CKE ODT CS_n VSS DQS_t DQS_c DQ[3:0] ZQ DQS_t DQS_c DQ[3:0] D31 DQS_t DQS_c DQ[3:0] CKE ODT CS_n VSS VSS CKE ODT CS_n CKE ODT CS_n ZQ ACT_n CKE1 D23 DQS15_t DQS15_c DQ[55:52] DQS_t DQS_c DQ[3:0] ZQ D29 DQS_t DQS_c DQ[3:0] ZQ D32 DQS_t DQS_c DQ[3:0] QABG[1:0] -> BG[1:0] : SDRAMs D[20:1] QBBG[1:0] -> BG[1:0] : SDRAMs D[36:21] QABA[1:0] -> BA[1:0] : SDRAMs D[20:1] QBBA[1:0] -> BA[1:0] : SDRAMs D[36:21] QAA[17:0] -> A[17:0] : SDRAMs D[20:1] QBA[17:0] -> A[17:0] : SDRAMs D[36:21] BA[1:0] CKE0 CKE ODT CS_n VSS VSS ZQ D35 DQS_t DQS_c DQ[3:0] ZQ R E G I S T E R QACKE1 -> CKE : SDRAMs D[20:11] QBCKE1 -> CKE : SDRAMs D[36:29] QAODT0 -> ODT : SDRAMs D[10:1] QBODT0 -> ODT : SDRAMs D[28:21] QAODT1 -> ODT : SDRAMs D[20:11] QBODT1 -> ODT : SDRAMs D[36:29] QACS0_n -> CS_n : SDRAMs D[10:1] QBCS0_n -> CS_n : SDRAMs D[28:21] QACS1_n -> CS_n : SDRAMs D[20:11] QBCS1_n -> CS_n : SDRAMs D[36:29] Y0_t -> CK_t : SDRAMs D[24:21], D[32:29] Y1_t -> CK_t : SDRAMs D[5:1], D[15:11] Y2_t -> CK_t : SDRAMs D[28:25], D[36:33] Y3_t -> CK_t : SDRAMs D[10:6], D[20:16] Y0_c -> CK_c : SDRAMs D[24:21], D[32:29] Y1_c -> CK_c: SDRAMs D[5:1], D[15:11] Y2_c -> CK_c : SDRAMs D[28:25], D[36:33] Y3_c -> CK_c : SDRAMs D[10:6], D[20:16] QRST_n -> RESET_n : All SDRAMs ERROR_IN_n - ALERT_n : All SDRAMs NOTE : 1. CK0_t, CK0_c terminated with 120 5% resistor. 2. CK1_t, CK1_c terminated with 120 5% resistor but not used. 3. Unless otherwise noted resistors are 22 5%. - 13 - VSS DQS_t DQS_c DQ[3:0] D22 DQS14_t DQS14_c DQ[47:44] DQS_t DQS_c DQ[3:0] ZQ VSS D28 DQS7_t DQS7_c DQ[59:56] ZQ VSS CKE ODT CS_n DQS_t DQS_c DQ[3:0] D34 DQS_t DQS_c DQ[3:0] CKE ODT CS_n D27 DQS6_t DQS6_c DQ[51:48] CKE ODT CS_n VSS ZQ ZQ DQS_t DQS_c DQ[3:0] ZQ D21 DQS13_t DQS13_c DQ[39:36] VSS DQS_t DQS_c DQ[3:0] CKE ODT CS_n DQS5_t DQS5_c DQ[43:40] D33 VSS D26 ZQ DQS_t DQS_c DQ[3:0] CKE ODT CS_n ZQ VSS CKE ODT CS_n DQS_t DQS_c DQ[3:0] CKE ODT CS_n D25 DQS4_t DQS4_c DQ[35:32] CKE ODT CS_n ZQ VSS CKE ODT CS_n QBCS1_n QBODT1 QBCKE1 Rev. 1.91 datasheet Registered DIMM DDR4 SDRAM 10. Absolute Maximum Ratings 10.1 Absolute Maximum DC Ratings [ Table 2 ] Absolute Maximum DC Ratings Symbol VDD VDDQ VPP VIN, VOUT TSTG Parameter Rating Units NOTE Voltage on VDD pin relative to Vss -0.3 ~ 1.5 V 1,3 Voltage on VDDQ pin relative to Vss -0.3 ~ 1.5 V 1,3 Voltage on VPP pin relative to Vss -0.3 ~ 3.0 V 4 Voltage on any pin except VREFCA to Vss -0.3 ~ 1.5 V 1,3 -55 to +100 C 1,2 Storage Temperature NOTE: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. 3. VDD and VDDQ must be within 300mV of each other at all times;and VREFCA must be not greater than 0.6 x VDDQ, When VDD and VDDQ are less than 500mV; VREFCA may be equal to or less than 300mV 4. VPP must be equal or greater than VDD/VDDQ at all times. 11. AC & DC Operating Conditions 11.1 Recommended DC Operating Conditions [ Table 3 ] Recommended DC Operating Conditions Symbol Parameter Rating Min. Typ. Max. Unit NOTE VDD Supply Voltage 1.14 1.2 1.26 V 1,2,3 VDDQ Supply Voltage for Output 1.14 1.2 1.26 V 1,2,3 VPP Peak-to-Peak Voltage 2.375 2.5 2.75 V 3 NOTE: 1. Under all conditions VDDQ must be less than or equal to VDD. 2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together. 3. DC bandwidth is limited to 20MHz. - 15 - Rev. 1.91 datasheet Registered DIMM DDR4 SDRAM 12. AC & DC Input Measurement Levels 12.1 AC & DC Logic Input Levels for Single-Ended Signals [ Table 4 ] Single-ended AC & DC Input Levels for Command and Address Symbol Parameter VIH.CA(DC75) DC input logic high VIL.CA(DC75) DC input logic low VIH.CA(AC100) AC input logic high DDR4-1600/1866/2133/2400 Min. DDR4-2666 Unit Max. Min. Max. VREFCA+ 0.075 VDD TBD TBD VSS VREFCA-0.075 TBD TBD V VREF + 0.1 Note 2 TBD TBD V NOTE V 1 VIL.CA(AC100) AC input logic low Note 2 VREF - 0.1 TBD TBD V 1 VREFCA(DC) Reference Voltage for ADD, CMD inputs 0.49*VDD 0.51*VDD TBD TBD V 2,3 NOTE: 1. See "Overshoot and Undershoot Specifications" on section. 2. The AC peak noise on VREFCA may not allow VREFCA to deviate from VREFCA(DC) by more than 1% VDD (for reference : approx. 12mV) 3. For reference : approx. VDD/2 12mV 12.2 AC and DC Input Measurement Levels: VREF Tolerances. The DC-tolerance limits and ac-noise limits for the reference voltages VREFCA is illustrated in Figure 1. It shows a valid reference voltage VREF(t) as a function of time. (VREF stands for VREFCA). VREF(DC) is the linear average of VREF(t) over a very long period of time (e.g. 1 sec). This average has to meet the min/max requirement in Table X. Furthermore VREF(t) may temporarily deviate from VREF(DC) by no more than 1% VDD. voltage VDD VSS time Figure 1. Illustration of VREF(DC) tolerance and VREF AC-noise limits The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC) and VIL(DC) are dependent on VREF. "VREF" shall be understood as VREF(DC), as defined in Figure 1. This clarifies, that DC-variations of VREF affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to which setup and hold is measured. System timing and voltage budgets need to account for VREF(DC) deviations from the optimum position within the data-eye of the input signals. This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated with VREF AC-noise. Timing and voltage effects due to AC-noise on VREF up to the specified limit (+/-1% of VDD) are included in DRAM timings and their associated deratings. - 16 - Rev. 1.91 datasheet Registered DIMM DDR4 SDRAM 12.3 AC and DC Logic Input Levels for Differential Signals 12.3.1 Differential Signals Definition tDVAC VIH.DIFF.AC.MIN Differential Input Voltage (CK-CK) (CK_t - CK_c) VIH.DIFF.MIN 0.0 half cycle VIL.DIFF.MAX VIL.DIFF.AC.MAX tDVAC time Figure 2. Definition of differential ac-swing and "time above ac-level" tDVAC NOTE: 1. Differential signal rising edge from VIL.DIFF.MAX to VIH.DIFF.MIN must be monotonic slope. 2. Differential signal falling edge from VIH.DIFF.MIN to VIL.DIFF.MAX must be monotonic slope. 12.3.2 Differential Swing Requirements for Clock (CK_t - CK_c) [ Table 5 ] Differential AC and DC Input Levels Symbol Parameter VIHdiff DDR4 -1600/1866/2133 DDR4 -2400/2666 unit NOTE NOTE 3 V 1 TBD V 1 2 x (VIH(AC) - VREF) NOTE 3 V 2 NOTE 3 2 x (VIL(AC) - VREF) V 2 min max min max differential input high +0.150 NOTE 3 TBD VILdiff differential input low NOTE 3 -0.150 NOTE 3 VIHdiff(AC) differential input high ac 2 x (VIH(AC) - VREF) NOTE 3 NOTE 3 2 x (VIL(AC) - VREF) VILdiff(AC) differential input low ac NOTE: 1. Used to define a differential signal slew-rate. 2. for CK_t - CK_c use VIH.CA/VIL.CA(AC) of ADD/CMD and VREFCA; 3. These values are not defined; however, the differential signals CK_t - CK_c, need to be within the respective limits (VIH.CA(DC) max, VIL.CA(DC)min) for single-ended signals as well as the limitations for overshoot and undershoot. [ Table 6 ] Allowed Time Before Ringback (tDVAC) for CK_t - CK_c Slew Rate [V/ns] tDVAC [ps] @ |VIH/Ldiff(AC)| = 200mV min max > 4.0 120 - 4.0 115 - 3.0 110 - 2.0 105 - 1.8 100 - 1.6 95 - 1.4 90 - 1.2 85 - 1.0 80 - < 1.0 80 - - 17 - Rev. 1.91 datasheet Registered DIMM DDR4 SDRAM 12.3.3 Single-ended Requirements for Differential Signals Each individual component of a differential signal (CK_t, CK_c) has also to comply with certain requirements for single-ended signals. CK_t and CK_c have to approximately reach VSEHmin / VSELmax (approximately equal to the ac-levels (VIH.CA(AC) / VIL.CA(AC)) for ADD/CMD signals) in every half-cycle. Note that the applicable ac-levels for ADD/CMD might be different per speed-bin etc. E.g., if Different value than VIH.CA(AC100)/VIL.CA(AC100) is used for ADD/CMD signals, then these ac-levels apply also for the single-ended signals CK_t and CK_c VDD or VDDQ VSEH min VSEH VDD/2 or VDDQ/2 CK VSEL max VSEL VSS or VSSQ time Figure 3. Single-ended requirement for differential signals. Note that, while ADD/CMD signal requirements are with respect to VrefCA, the single-ended components of differential signals have a requirement with respect to VDD / 2; this is nominally the same. The transition of single-ended signals through the ac-levels is used to measure setup time. For singleended components of differential signals the requirement to reach VSELmax, VSEHmin has no bearing on timing, but adds a restriction on the common mode characteristics of these signals. [ Table 7 ] Single-ended Levels for CK_t, CK_c Symbol Parameter VSEH VSEL DDR4-1600/1866/2133 DDR4-2400/2666 Unit NOTE NOTE3 V 1, 2 TBD V 1, 2 Min Max Min Max Single-ended high-level for CK_t , CK_c (VDD/2)+0.100 NOTE3 TBD Single-ended low-level for CK_t , CK_c NOTE3 (VDD/2)-0.100 NOTE3 NOTE: 1. For CK_t - CK_c use VIH.CA/VIL.CA(AC) of ADD/CMD; 2. VIH(AC)/VIL(AC) for ADD/CMD is based on VREFCA; 3. These values are not defined, however the single-ended signals CK_t - CK_c need to be within the respective limits (VIH.CA(DC) max, VIL.CA(DC)min) for single-ended signals as well as the limitations for overshoot and undershoot. - 18 - Rev. 1.91 datasheet Registered DIMM DDR4 SDRAM 12.4 Slew Rate Definitions 12.4.1 Slew Rate Definitions for Differential Input Signals (CK) [ Table 8 ] Differential Input Slew Rate Definition Description from Differential input slew rate for rising edge(CK_t - CK_c) V Differential input slew rate for falling edge(CK_t - CK_c) V ILdiffmax IHdiffmin Defined by to V IHdiffmin V V IHdiffmin - ILdiffmax DeltaTRdiff V V V IHdiffmin - ILdiffmax DeltaTFdiff ILdiffmax NOTE: The differential signal (i,e.,CK_t - CK_c) must be linear between these thresholds. Differential Input Voltage(i,e, CK_t - CK_c) Delta TRdiff V IHdiffmin 0 V Delta TFdiff Figure 4. Differential Input Slew Rate Definition for CK_t, CK_c - 19 - ILdiffmax Rev. 1.91 datasheet Registered DIMM DDR4 SDRAM 12.5 Differential Input Cross Point Voltage To guarantee tight setup and hold times as well as output skew parameters with respect to clock, each cross point voltage of differential input signals (CK_t, CK_c) must meet the requirements in Table 9. The differential input cross point voltage VIX is measured from the actual cross point of true and complement signals to the midlevel between of VDD and VSS. VDD CK_t Vix VDD/2 Vix CK_c VSEL VSEH VSS Figure 5. Vix Definition (CK) [ Table 9 ] Cross Point Voltage for Differential Input Signals (CK) Symbol DDR4-1600/1866/2133 Parameter min max - Area of VSEH, VSEL VSEL =< VDD/2 145mV VDD/2 - 145mV =< VSEL =< VDD/2 100mV VlX(CK) Differential Input Cross Point Voltage relative to VDD/2 for CK_t, CK_c -120mV -(VDD/2 - VSEL) + 25mV Symbol Parameter VDD/2 + 100mV =< VSEH =< VDD/ 2 + 145mV VDD/2 + 145mV =< VSEH (VSEH - VDD/2) 25mV 120mV DDR4-2400/2666 min max - Area of VSEH, VSEL TBD TBD TBD TBD VlX(CK) Differential Input Cross Point Voltage relative to VDD/2 for CK_t, CK_c TBD TBD TBD TBD - 20 - Rev. 1.91 datasheet Registered DIMM DDR4 SDRAM 12.6 Single-ended AC & DC Output Levels [ Table 10 ] Single-ended AC & DC Output Levels Symbol Parameter DDR4-1600/1866/2133/2400/2666 Units VOH(DC) DC output high measurement level (for IV curve linearity) 1.1 x VDDQ V VOM(DC) DC output mid measurement level (for IV curve linearity) 0.8 x VDDQ V VOL(DC) DC output low measurement level (for IV curve linearity) 0.5 x VDDQ V NOTE VOH(AC) AC output high measurement level (for output SR) (0.7 - 0.15) x VDDQ V 1 VOL(AC) AC output low measurement level (for output SR) (0.7 - 0.15) x VDDQ V 1 NOTE: 1. The swing of 0.15 x VDDQ is based on approximately 50% of the static single-ended output peak-to-peak swing with a driver impedance of RZQ/7 and an effective test load of 50 to VTT = VDDQ. 12.7 Differential AC & DC Output Levels [ Table 11 ] Differential AC & DC Output Levels DDR4-1600/1866/2133/2400/2666 Units NOTE VOHdiff(AC) Symbol Parameter AC differential output high measurement level (for output SR) +0.3 x VDDQ V 1 VOLdiff(AC) AC differential output low measurement level (for output SR) -0.3 x VDDQ V 1 NOTE: 1. The swing of 0.3 x VDDQ is based on approximately 50% of the static differential output peak-to-peak swing with a driver impedance of RZQ/7 and an effective test load of 50 to VTT = VDDQ at each of the differential outputs. 12.8 Single-ended Output Slew Rate With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC) for single ended signals as shown in Table 12 and Figure 6. [ Table 12 ] Single-ended Output Slew Rate Definition Measured Description Defined by From To Single ended output slew rate for rising edge VOL(AC) VOH(AC) [VOH(AC)-VOL(AC)] / Delta TRse Single ended output slew rate for falling edge VOH(AC) VOL(AC) [VOH(AC)-VOL(AC)] / Delta TFse NOTE: 1. Output slew rate is verified by design and characterization, and may not be subject to production test. VOH(AC) VTT VOL(AC) delta TFse delta TRse Figure 6. Single-ended Output Slew Rate Definition - 21 - Rev. 1.91 datasheet Registered DIMM DDR4 SDRAM [ Table 13 ] Single-ended Output Slew Rate Parameter Single ended output slew rate Symbol DDR4-1600 DDR4-1866 DDR4-2133 DDR4-2400 DDR4-2666 Min Max Min Max Min Max Min Max Min Max 4 9 4 9 4 9 4 9 4 9 SRQse Units V/ns Description: SR: Slew Rate Q: Query Output (like in DQ, which stands for Data-in, Query-Output) se: Single-ended Signals For Ron = RZQ/7 setting NOTE: 1. In two cases, a maximum slew rate of 12 V/ns applies for a single DQ signal within a byte lane. -Case 1 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high to low or low to high) while all remaining DQ signals in the same byte lane are static (i.e. they stay at either high or low). -Case 2 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high to low or low to high) while all remaining DQ signals in the same byte lane are switching into the opposite direction (i.e. from low to high or high to low respectively). For the remaining DQ signal switching into the opposite direction, the regular maximum limit of 9 V/ns applies 12.9 Differential Output Slew Rate With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOLdiff(AC) and VOHdiff(AC) for differential signals as shown in Table 14 and Figure 7. [ Table 14 ] Differential Output Slew Rate Definition Measured Description Defined by From To Differential output slew rate for rising edge VOLdiff(AC) VOHdiff(AC) [VOHdiff(AC)-VOLdiff(AC)] / Delta TRdiff Differential output slew rate for falling edge VOHdiff(AC) VOLdiff(AC) [VOHdiff(AC)-VOLdiff(AC)] / Delta TFdiff NOTE: 1. Output slew rate is verified by design and characterization, and may not be subject to production test. VOHdiff(AC) VTT VOLdiff(AC) delta TFdiff delta TRdiff Figure 7. Differential Output Slew Rate Definition [ Table 15 ] Differential Output Slew Rate Parameter Differential output slew rate Symbol SRQdiff DDR4-1600 DDR4-1866 DDR4-2133 DDR4-2400 DDR4-2666 Min Max Min Max Min Max Min Max Min Max 8 18 8 18 8 18 8 18 8 18 Description: SR: Slew Rate Q: Query Output (like in DQ, which stands for Data-in, Query-Output) diff: Differential Signals For Ron = RZQ/7 setting - 22 - Units V/ns Rev. 1.91 datasheet Registered DIMM DDR4 SDRAM 12.10 Single-ended AC & DC Output Levels of Connectivity Test Mode Following output parameters will be applied for DDR4 SDRAM Output Signal during Connectivity Test Mode. [ Table 16 ] Single-ended AC & DC Output Levels of Connectivity Test Mode Symbol Parameter DDR4-1600/1866/2133/2400/2666 Unit Notes VOH(DC) DC output high measurement level (for IV curve linearity) 1.1 x VDDQ V VOM(DC) DC output mid measurement level (for IV curve linearity) 0.8 x VDDQ V VOL(DC) DC output low measurement level (for IV curve linearity) 0.5 x VDDQ V VOB(DC) DC output below measurement level (for IV curve linearity) 0.2 x VDDQ V VOH(AC) AC output high measurement level (for output SR) VTT + (0.1 x VDDQ) V 1 VOL(AC) AC output below measurement level (for output SR) VTT - (0.1 x VDDQ) V 1 NOTE: 1. The effective test load is 50 terminated by VTT = 0.5 * VDDQ. VOH(AC) VTT VOL(AC) TR_output_CT TR_output_CT Figure 8. Output Slew Rate Definition of Connectivity Test Mode [ Table 17 ] Single-ended Output Slew Rate of Connectivity Test Mode Parameter DDR4-1600/1866/2133/2400/2666 Symbol Min Max Unit Output signal Falling time TF_output_CT - 10 ns/V Output signal Rising time TR_output_CT - 10 ns/V 12.11 Test Load for Connectivity Test Mode Timing The reference load for ODT timings is defined in Figure 9. VDDQ CT_INPUTS DQ, DM DQSL_t , DQSL_c DQSU_t , DQSU_c DQS_t , DQS_c DUT Rterm = 50 ohm VSSQ Timing Reference Points Figure 9. Connectivity Test Mode Timing Reference Load - 23 - 0.5*VDDQ Notes Registered DIMM datasheet Rev. 1.91 DDR4 SDRAM 13. DIMM IDD Specification Definition [ Table 18 ] Basic IDD, IPP and IDDQ Measurement Conditions Symbol Description Operating One Bank Active-Precharge Current (AL=0) IDD0 CKE: High; External clock: On; tCK, nRC, nRAS, CL: Refer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n: High between ACT and PRE; Command, Address, Bank Group Address, Bank Address Inputs: partially toggling; Data IO: VDDQ; DM_n: stable at 1; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,...; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern IDD0A IPP0 Operating One Bank Active-Precharge Current (AL=CL-1) AL = CL-1, Other conditions: see IDD0 Operating One Bank Active-Precharge IPP Current Same condition with IDD0 Operating One Bank Active-Read-Precharge Current (AL=0) IDD1 CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: Refer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n: High between ACT, RD and PRE; Command, Address, Bank Group Address, Bank Address Inputs, Data IO: partially toggling; DM_n: stable at 1; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,...; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern IDD1A IPP1 Operating One Bank Active-Read-Precharge Current (AL=CL-1) AL = CL-1, Other conditions: see IDD1 Operating One Bank Active-Read-Precharge IPP Current Same condition with IDD1 Precharge Standby Current (AL=0) IDD2N CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n: stable at 1; Command, Address, Bank Group Address, Bank Address Inputs: partially toggling; Data IO: VDDQ; DM_n: stable at 1; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern IDD2NA IPP2N Precharge Standby Current (AL=CL-1) AL = CL-1, Other conditions: see IDD2N Precharge Standby IPP Current Same condition with IDD2N Precharge Standby ODT Current IDD2NT CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n: stable at 1; Command, Address, Bank Group Address, Bank Address Inputs: partially toggling; Data IO: VSSQ; DM_n: stable at 1; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: toggling according; Pattern Details: Refer to Component Datasheet for detail pattern IDDQ2NT Precharge Standby ODT IDDQ Current (Optional) Same definition like for IDD2NT, however measuring IDDQ current instead of IDD current IDD2NL IDD2NG IDD2ND IDD2N_par IDD2P Precharge Standby Current with CAL enabled Same definition like for IDD2N, CAL enabled3 Precharge Standby Current with Gear Down mode enabled Same definition like for IDD2N, Gear Down mode enabled3,5 Precharge Standby Current with DLL disabled Same definition like for IDD2N, DLL disabled3 Precharge Standby Current with CA parity enabled Same definition like for IDD2N, CA parity enabled3 Precharge Power-Down Current CKE: Low; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n: stable at 1; Command, Address, Bank Group Address, Bank Address Inputs: stable at 0; Data IO: VDDQ; DM_n: stable at 1; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: stable at 0 IPP2P Precharge Power-Down IPP Current Same condition with IDD2P IDD2Q Precharge Quiet Standby Current CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n: stable at 1; Command, Address, Bank Group Address, Bank Address Inputs: stable at 0; Data IO: VDDQ; DM_n: stable at 1;Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: stable at 0 - 24 - Registered DIMM datasheet Rev. 1.91 DDR4 SDRAM Symbol Description IDD3N Active Standby Current CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n: stable at 1; Command, Address, Bank Group Address, Bank Address Inputs: partially toggling; Data IO: VDDQ; DM_n: stable at 1;Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: stable at 0; Pattern Details:Refer to Component Datasheet for detail pattern IDD3NA Active Standby Current (AL=CL-1) AL = CL-1, Other conditions: see IDD3N IPP3N Active Standby IPP Current Same condition with IDD3N IDD3P Active Power-Down Current CKE: Low; External clock: On; tCK, CL: sRefer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n: stable at 1; Command, Address, Bank Group Address, Bank Address Inputs: stable at 0; Data IO: VDDQ; DM_n: stable at 1; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: stable at 0 IPP3P Active Power-Down IPP Current Same condition with IDD3P IDD4R Operating Burst Read Current CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern; BL: 82; AL: 0; CS_n: High between RD; Command, Address, Bank Group Address, Bank Address Inputs: partially toggling; Data IO: seamless read data burst with different data between one burst and the next one according; DM_n: stable at 1; Bank Activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,...; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern IDD4RA Operating Burst Read Current (AL=CL-1) AL = CL-1, Other conditions: see IDD4R IDD4RB Operating Burst Read Current with Read DBI Read DBI enabled3, Other conditions: see IDD4R IPP4R Operating Burst Read IPP Current Same condition with IDD4R IDDQ4R (Optional) Operating Burst Read IDDQ Current Same definition like for IDD4R, however measuring IDDQ current instead of IDD current IDDQ4RB (Optional) Operating Burst Read IDDQ Current with Read DBI Same definition like for IDD4RB, however measuring IDDQ current instead of IDD current IDD4W Operating Burst Write Current CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n: High between WR; Command, Address, Bank Group Address, Bank Address Inputs: partially toggling; Data IO: seamless write data burst with different data between one burst and the next one; DM_n: stable at 1; Bank Activity: all banks open, WR commands cycling through banks: 0,0,1,1,2,2,...; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: stable at HIGH; Pattern Details: Refer to Component Datasheet for detail pattern IDD4WA Operating Burst Write Current (AL=CL-1) AL = CL-1, Other conditions: see IDD4W IDD4WB Operating Burst Write Current with Write DBI Write DBI enabled3, Other conditions: see IDD4W IDD4WC Operating Burst Write Current with Write CRC Write CRC enabled3, Other conditions: see IDD4W IDD4W_par Operating Burst Write Current with CA Parity CA Parity enabled3, Other conditions: see IDD4W IPP4W Operating Burst Write IPP Current Same condition with IDD4W IDD5B Burst Refresh Current (1X REF) CKE: High; External clock: On; tCK, CL, nRFC: Refer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n: High between REF; Command, Address, Bank Group Address, Bank Address Inputs: partially toggling; Data IO: VDDQ; DM_n: stable at 1; Bank Activity: REF command every nRFC; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern IPP5B Burst Refresh Write IPP Current (1X REF) Same condition with IDD5B IDD5F2 Burst Refresh Current (2X REF) tRFC=tRFC_x2, Other conditions: see IDD5B IPP5F2 Burst Refresh Write IPP Current (2X REF) Same condition with IDD5F2 - 25 - Registered DIMM datasheet Symbol Rev. 1.91 DDR4 SDRAM Description IDD5F4 Burst Refresh Current (4X REF) tRFC=tRFC_x4, Other conditions: see IDD5B IPP5F4 Burst Refresh Write IPP Current (4X REF) Same condition with IDD5F4 IDD6N Self Refresh Current: Normal Temperature Range TCASE: 0 - 85C; Low Power Array Self Refresh (LP ASR): Normal4; CKE: Low; External clock: Off; CK_t and CK_c#: LOW; CL: Refer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n#, Command, Address, Bank Group Address, Bank Address, Data IO: High; DM_n: stable at 1; Bank Activity: Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: MIDLEVEL IPP6N Self Refresh IPP Current: Normal Temperature Range Same condition with IDD6N IDD6E Self-Refresh Current: Extended Temperature Range TCASE: 0 - 95C; Low Power Array Self Refresh (LP ASR): Extended4; CKE: Low; External clock: Off; CK_t and CK_c: LOW; CL: Refer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n, Command, Address, Bank Group Address, Bank Address, Data IO: High; DM_n:stable at 1; Bank Activity: Extended Temperature Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: MID-LEVEL IPP6E Self Refresh IPP Current: Extended Temperature Range Same condition with IDD6E IDD6R Self-Refresh Current: Reduced Temperature Range TCASE: 0 - 45C; Low Power Array Self Refresh (LP ASR): Reduced4; CKE: Low; External clock: Off; CK_t and CK_c#: LOW; CL: Refer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n#, Command, Address, Bank Group Address, Bank Address, Data IO: High; DM_n:stable at 1; Bank Activity: Extended Temperature Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: MID-LEVEL IPP6R Self Refresh IPP Current: Reduced Temperature Range Same condition with IDD6R IDD6A Auto Self-Refresh Current TCASE: 0 - 95C; Low Power Array Self Refresh (LP ASR): Auto4; CKE: Low; External clock: Off; CK_t and CK_c#: LOW; CL: Refer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n#, Command, Address, Bank Group Address, Bank Address, Data IO: High; DM_n:stable at 1; Bank Activity: Auto Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: MID-LEVEL IPP6A Auto Self-Refresh IPP Current Same condition with IDD6A IDD7 Operating Bank Interleave Read Current CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: Refer to Component Datasheet for detail pattern; BL: 81; AL: CL-1; CS_n: High between ACT and RDA; Command, Address, Bank Group Address, Bank Address Inputs: partially toggling; Data IO: read data bursts with different data between one burst and the next one; DM_n: stable at 1; Bank Activity: two times interleaved cycling through banks (0, 1, ...7) with different addressing; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern IPP7 Operating Bank Interleave Read IPP Current Same condition with IDD7 IDD8 Maximum Power Down Current TBD IPP8 Maximum Power Down IPP Current Same condition with IDD8 NOTE: 1. Burst Length: BL8 fixed by MRS: set MR0 [A1:0=00]. 2. Output Buffer Enable - set MR1 [A12 = 0]: Qoff = Output buffer enabled - set MR1 [A2:1 = 00]: Output Driver Impedance Control = RZQ/7 RTT_Nom enable - set MR1 [A10:8 = 011]: RTT_NOM = RZQ/6 RTT_WR enable - set MR2 [A10:9 = 01]: RTT_WR = RZQ/2 RTT_PARK disable - set MR5 [A8:6 = 000] 3. CAL enabled: set MR4 [A8:6 = 001]: 1600MT/s 010]: 1866MT/s, 2133MT/s 011]: 2400MT/s, 2666MT/s Gear Down mode enabled: set MR3 [A3 = 1]: 1/4 Rate DLL disabled: set MR1 [A0 = 0] CA parity enabled: set MR5 [A2:0 = 001]: 1600MT/s,1866MT/s, 2133MT/s 010]: 2400MT/s, 2666MT/s Read DBI enabled: set MR5 [A12 = 1] Write DBI enabled: set MR5 [A11 = 1] 4. Low Power Array Self Refresh (LP ASR): set MR2 [A7:6 = 00]: Normal 01]: Reduced Temperature range 10]: Extended Temperature range 11]: Auto Self Refresh 5. IDD2NG should be measured after sync pules (NOP) input. - 26 - Rev. 1.91 datasheet Registered DIMM DDR4 SDRAM 14. IDD SPEC Table IDD and IPP values are for typical operating range of voltage and temperature unless otherwise noted. [ Table 19 ] IDD and IDDQ Specification M393A1K43BB0 : 8GB(1Gx72) Module Symbol DDR4-2133 DDR4-2400 DDR4-2666 15-15-15 17-17-17 19-19-19 Unit VDD 1.2V VPP 2.5V VDD 1.2V VPP 2.5V VDD 1.2V VPP 2.5V IDD Max. IPP Max. IDD Max. IPP Max. IDD Max. IPP Max. IDD0 590 36 605 36 620 36 mA IDD0A 602 36 628 36 638 36 mA mA IDD1 804 36 824 36 838 36 IDD1A 822 36 847 36 873 36 mA IDD2N 486 27 504 27 511 27 mA IDD2NA 510 27 532 27 544 27 mA IDD2NT 505 27 528 27 539 27 mA IDD2NL 442 27 459 27 466 27 mA IDD2NG 488 27 506 27 523 27 mA IDD2ND 473 27 490 27 504 27 mA IDD2N_par 504 27 521 27 530 27 mA IDD2P 305 27 314 27 320 27 mA IDD2Q 474 27 491 27 498 27 mA IDD3N 573 27 591 27 605 27 mA IDD3NA 593 27 613 27 633 27 mA IDD3P 348 27 360 27 365 27 mA IDD4R 1264 27 1323 27 1398 27 mA IDD4RA 1294 27 1358 27 1439 27 mA IDD4RB 1270 27 1339 27 1407 27 mA IDD4W 1121 27 1181 27 1250 27 mA IDD4WA 1156 27 1216 27 1290 27 mA IDD4WB 1122 27 1183 27 1252 27 mA IDD4WC 1063 27 1130 27 1200 27 mA IDD4W_par 1195 27 1269 27 1358 27 mA IDD5B 2055 162 2070 162 2212 162 mA IDD5F2 1566 135 1587 135 1681 135 mA IDD5F4 1385 126 1405 126 1482 126 mA IDD6N 214 36 214 36 225 36 mA IDD6E 307 45 306 45 318 54 mA IDD6R 168 32 167 32 174 36 mA IDD6A 211 36 210 36 219 36 mA IDD7 1603 72 1613 77 1731 81 mA IDD8 101 27 101 27 109 27 mA NOTE : 1. DIMM IDD SPEC is based on the condition that de-actived rank (IDLE) is IDD2N. Please refer to Table 20. 2. IDD current measure method and detail patterns are described on DDR4 component datasheet. 3. VDD and VDDQ are merged on module PCB (IDDQ values are not considered by Qoff condition) 4. DIMM IDD Values are calculated based on the component IDD spec and Register power. - 26 - NOTE Rev. 1.91 datasheet Registered DIMM DDR4 SDRAM 16GB(2Gx72) Module M393A2K40BB0 M393A2K40BB1 M393A2K40BB2 DDR4-2133 DDR4-2400 DDR4-2666 15-15-15 17-17-17 19-19-19 Symbol IDD0 Unit VDD 1.2V VPP 2.5V VDD 1.2V VPP 2.5V VDD 1.2V VPP 2.5V IDD Max. IPP Max. IDD Max. IPP Max. IDD Max. IPP Max. 905 72 953 72 987 72 mA IDD0A 929 72 999 72 1040 72 mA IDD1 1186 72 1246 72 1339 72 mA IDD1A 1223 72 1292 72 1357 72 mA IDD2N 698 54 749 54 756 54 mA IDD2NA 747 54 806 54 809 54 mA IDD2NT 732 54 793 54 808 54 mA IDD2NL 613 54 656 54 669 54 mA IDD2NG 702 54 754 54 754 54 mA IDD2ND 674 54 722 54 719 54 mA IDD2N_par 735 54 785 54 791 54 mA IDD2P 460 54 492 54 496 54 mA IDD2Q 675 54 723 54 739 54 mA IDD3N 856 54 928 54 987 54 mA IDD3NA 895 54 972 54 1023 54 mA IDD3P 537 54 586 54 592 54 mA IDD4R 1860 54 2041 54 2263 54 mA IDD4RA 1919 54 2110 54 2353 54 mA IDD4RB 1882 54 2067 54 2298 54 mA IDD4W 1771 54 1959 54 2146 54 mA IDD4WA 1836 54 2031 54 2221 54 mA IDD4WB 1771 54 1960 54 2146 54 mA IDD4WC 1730 54 1852 54 2011 54 mA IDD4W_par 1917 54 2132 54 2325 54 mA IDD5B 3706 324 3782 324 4159 324 mA IDD5F2 2750 270 2818 270 3040 270 mA IDD5F4 2381 252 2445 252 2642 252 mA IDD6N 374 72 404 72 443 72 mA IDD6E 562 90 596 90 628 90 mA IDD6R 282 63 308 63 322 63 mA IDD6A 364 72 388 72 423 72 mA IDD7 3297 144 3648 153 4221 162 mA IDD8 160 54 181 54 200 54 mA NOTE : 1. DIMM IDD SPEC is based on the condition that de-actived rank (IDLE) is IDD2N. Please refer to Table 20. 2. IDD current measure method and detail patterns are described on DDR4 component datasheet. 3. VDD and VDDQ are merged on module PCB ( IDDQ values are not considered by Qoff condition) 4. DIMM IDD Values are calculated based on the component IDD spec and Register power. - 27 - NOTE Rev. 1.91 datasheet Registered DIMM DDR4 SDRAM 32GB(4Gx72) Module M393A4K40BB0 M393A4K40BB1 M393A4K40BB2 DDR4-2133 DDR4-2400 DDR4-2666 15-15-15 17-17-17 19-19-19 Symbol Unit VDD 1.2V VPP 2.5V VDD 1.2V VPP 2.5V VDD 1.2V VPP 2.5V IDD Max. IPP Max. IDD Max. IPP Max. IDD Max. IPP Max. IDD0 1356 126 1438 126 1510 126 mA IDD0A 1379 126 1485 126 1563 126 mA IDD1 1667 126 1772 126 1903 126 mA IDD1A 1704 126 1819 126 1920 126 mA IDD2N 1189 108 1276 108 1300 108 mA IDD2NA 1247 108 1349 108 1404 108 mA IDD2NT 1216 108 1323 108 1402 108 mA IDD2NL 979 108 1049 108 1084 108 mA IDD2NG 1156 108 1244 108 1296 108 mA IDD2ND 1100 108 1180 108 1224 108 mA IDD2N_par 1221 108 1307 108 1328 108 mA IDD2P 598 108 652 108 723 108 mA IDD2Q 1103 108 1182 108 1224 108 mA IDD3N 1461 108 1591 108 1759 108 mA IDD3NA 1537 108 1678 108 1831 108 mA IDD3P 748 108 840 108 873 108 mA IDD4R 2341 108 2568 108 2827 108 mA IDD4RA 2400 108 2637 108 2916 108 mA IDD4RB 2363 108 2593 108 2862 108 mA IDD4W 2252 108 2486 108 2710 108 mA IDD4WA 2317 108 2557 108 2784 108 mA IDD4WB 2252 108 2486 108 2709 108 mA IDD4WC 2210 108 2379 108 2574 108 mA IDD4W_par 2397 108 2658 108 2888 108 mA IDD5B 4187 378 4308 378 4722 378 mA IDD5F2 3231 324 3344 324 3604 324 mA IDD5F4 2862 306 2971 306 3206 306 mA IDD6N 734 144 796 144 881 144 mA IDD6E 1108 180 1178 180 1250 180 mA IDD6R 550 126 603 126 638 126 mA IDD6A 714 144 763 144 840 144 mA IDD7 3778 198 4175 207 4786 216 mA IDD8 317 108 360 108 405 108 mA NOTE : 1. DIMM IDD SPEC is based on the condition that de-actived rank (IDLE) is IDD2N. Please refer to Table 20. 2. IDD current measure method and detail patterns are described on DDR4 component datasheet. 3. VDD and VDDQ are merged on module PCB ( IDDQ values are not considered by Qoff condition) 4. DIMM IDD Values are calculated based on the component IDD spec and Register power. - 28 - NOTE datasheet Registered DIMM [ Table 20 ] DIMM Rank Status SEC DIMM Operating Rank The other Rank IDD0 IDD0 IDD2N IDD2N IDD1 IDD1 IDD2P IDD2P IDD2P IDD2N IDD2N IDD2N IDD2Q IDD2Q IDD2Q IDD3P IDD3P IDD3P IDD3N IDD3N IDD3N IDD4R IDD4R IDD2N IDD4W IDD4W IDD2N IDD5B IDD5B IDD2N IDD6 IDD6 IDD6 IDD7 IDD7 IDD2N IDD8 IDD8 IDD8 - 29 - Rev. 1.91 DDR4 SDRAM Rev. 1.91 datasheet Registered DIMM DDR4 SDRAM 15. Input/Output Capacitance [ Table 21 ] Silicon Pad I/O Capacitance Symbol Parameter CIO DDR4-1600/1866/2133 DDR4-2400/2666 Unit NOTE 1.15 pF 1,2,3 -0.1 0.1 pF 1,2,3,11 0.05 - 0.05 pF 1,2,3,5 0.8 0.2 0.7 pF 1,3 min max min max Input/output capacitance 0.55 1.4 0.55 CDIO Input/output capacitance delta -0.1 0.1 CDDQS Input/output capacitance delta DQS_t and DQS_c - CCK Input capacitance, CK_t and CK_c 0.2 CDCK Input capacitance delta CK_t and CK_c - 0.05 - 0.05 pF 1,3,4 CI Input capacitance (CTRL, ADD, CMD pins only) 0.2 0.8 0.2 0.7 pF 1,3,6 CDI_ CTRL Input capacitance delta (All CTRL pins only) -0.1 0.1 -0.1 0.1 pF 1,3,7,8 CDI_ ADD_CMD Input capacitance delta (All ADD/CMD pins only) -0.1 0.1 -0.1 0.1 pF 1,2,9,10 CALERT Input/output capacitance of ALERT 0.5 1.5 0.5 1.5 pF 1,3 CZQ Input/output capacitance of ZQ - 2.3 - 2.3 pF 1,3,12 CTEN Input capacitance of TEN 0.2 2.3 0.2 2.3 pF 1,3,13 NOTE: 1. This parameter is not subject to production test. It is verified by design and characterization. The silicon only capacitance is validated by de-embedding the package L & C parasitic. The capacitance is measured with VDD, VDDQ, VSS, VSSQ applied with all other signal pins floating. Measurement procedure tbd. 2. DQ, DM_n, DQS_T, DQS_c, TDQS_T, TDQS_C. Although the DM, TDQS_T and TDQS_C pins have different functions, the loading matches DQ and DQS 3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here 4. Absolute value CK_T-CK_C 5. Absolute value of CIO(DQS_T)-CIO (DQS_c) 6. CI applies to ODT, CS_n, CKE, A0-A17, BA0-BA1, BG0-BG1, RAS_n/A16, CAS_n/A15, WE_n/A14, ACT_n and PAR. 7. CDI CTRL applies to ODT, CS_n and CKE 8. CDI_CTRL = CI(CTRL)-0.5*(CI(CLK_T)+CI(CLK_C)) 9. CDI_ADD_ CMD applies to, A0-A17, BA0-BA1, BG0-BG1,RAS_n/A16, CAS_n/A15, WE_n/A14, ACT_n and PAR. 10. CDI_ADD_CMD = CI(ADD_CMD)-0.5*(CI(CLK_T)+CI(CLK_C)) 11. CDIO = CIO(DQ,DM)-0.5*(CIO(DQS_T)+CIO(DQS_c)) 12. Maximum external load capacitance on ZQ pin: tbd pF. 13.TEN pin may be DRAM internally pulled low through a weak pull-down resistor to VSS. In this case CTEN might not be valid and system shall verify TEN signal with Vendor specific information. - 31 - Rev. 1.91 datasheet Registered DIMM DDR4 SDRAM 16. Electrical Characterisitics and AC Timing 16.1 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin [ Table 22 ] DDR4-1600 Speed Bins and Operations Speed Bin DDR4-1600 CL-nRCD-nRP 11-11-11 Parameter Symbol tAA Internal read command to first data with read DBI enabled tAA_DBI ACT to internal read or write delay time tRCD PRE command period tRP ACT to PRE command period tRAS ACT to ACT or REF command period CWL = 9 CWL = 9,11 NOTE 18.00 ns 11 tAA(max) +2nCK ns 11 - ns 11 - ns 11 9 x tREFI ns 11 - ns 11 1.6 ns 1,2,3,4,10,13 ns 1,2,3,4,10 ns 1,2,3,4 ns 1,2,3,4 min 13.75 Internal read command to first data Unit max 13 (13.50)5,11 tAA(min) + 2nCK 13.7513 (13.50)5,11 13.7513 (13.50)5,11 35 48.75 tRC (48.50)5,11 Normal Read DBI CL = 9 CL = 11 tCK(AVG) CL = 10 CL = 12 tCK(AVG) CL = 10 CL = 12 tCK(AVG) CL = 11 CL = 13 tCK(AVG) 1.25 CL = 12 CL = 14 tCK(AVG) 1.25 1.5 (Optional)5,11 Reserved Reserved <1.5 ns 1,2,3 Supported CL Settings 9,11,12 nCK 12,13 Supported CL Settings with read DBI 11,13,14 nCK 12 Supported CWL Settings 9,11 nCK - 32 - <1.5 Rev. 1.91 datasheet Registered DIMM DDR4 SDRAM [ Table 23 ] DDR4-1866 Speed Bins and Operations Speed Bin DDR4-1866 CL-nRCD-nRP 13-13-13 Parameter Symbol Internal read command to first data tAA Internal read command to first data with read DBI enabled tAA_DBI ACT to internal read or write delay time tRCD PRE command period tRP ACT to PRE command period tRAS ACT to ACT or REF command period CWL = 9 CWL = 9,11 CWL = 10,12 Read DBI CL = 9 CL = 11 tCK(AVG) CL = 10 CL = 12 tCK(AVG) CL = 10 CL = 12 tCK(AVG) CL = 11 CL = 13 NOTE 18.00 ns 11 tAA(max) +2nCK ns 11 - ns 11 - ns 11 9 x tREFI ns 11 - ns 11 1.6 ns 1,2,3,4,10,13 ns 1,2,3,4,10 ns 4 ns 1,2,3,4,6 ns 1,2,3,6 ns 1,2,3,4 min max 13.9213 (13.50)5,11 tAA(min) + 2nCK 13.9213 (13.50)5,11 13.9213 (13.50)5,11 34 47.92 tRC Normal Unit (47.50)5,11 1.5 (Optional)5,11 Reserved Reserved 1.25 tCK(AVG) <1.5 (Optional)5,11 CL = 12 CL = 14 tCK(AVG) CL = 12 CL = 14 tCK(AVG) 1.25 <1.5 CL = 13 CL = 15 tCK(AVG) 1.071 <1.25 ns 1,2,3,4 CL = 14 CL = 16 tCK(AVG) 1.071 <1.25 ns 1,2,3 Reserved Supported CL Settings 9,11,12,13,14 nCK 12,13 Supported CL Settings with read DBI 11,13,14,15,16 nCK 12 Supported CWL Settings 9,10,11,12 nCK - 33 - Rev. 1.91 datasheet Registered DIMM DDR4 SDRAM [ Table 24 ] DDR4-2133 Speed Bins and Operations Speed Bin DDR4-2133 CL-nRCD-nRP 15-15-15 Parameter Symbol Internal read command to first data tAA Internal read command to first data with read DBI enabled tAA_DBI ACT to internal read or write delay time tRCD PRE command period tRP ACT to PRE command period tRAS ACT to ACT or REF command period tRC CWL = 9 CWL = 9,11 CWL = 10,12 CWL = 11,14 Unit NOTE 18.00 ns 11 tAA(max) + 3nCK ns 11 - ns 11 - ns 11 9 x tREFI ns 11 - ns 11 1.6 ns 1,2,3,4,10,1 3 ns 1,2,3,10 ns 1,2,3,4,7 ns 1,2,3,7 ns 1,2,3,4,7 ns 1,2,3,7 ns 1,2,3,4 min max 14.0613 (13.75)5,11 tAA(min) + 3nCK 14.06 (13.75)5,11 14.06 (13.75)5,11 33 47.06 (46.75)5,11 Normal Read DBI CL = 9 CL = 11 tCK(AVG) CL = 10 CL = 12 tCK(AVG) CL = 11 CL = 13 tCK(AVG) CL = 12 CL = 14 tCK(AVG) CL = 13 CL = 15 tCK(AVG) CL = 14 CL = 16 tCK(AVG) CL = 14 CL = 17 tCK(AVG) CL = 15 CL = 18 tCK(AVG) 0.937 <1.071 ns 1,2,3,4 CL = 16 CL = 19 tCK(AVG) 0.937 <1.071 ns 1,2,3 12,13 1.5 (Optional)5,11 Reserved 1.25 <1.5 (Optional) 5,11 1.25 <1.5 1.071 <1.25 (Optional)5,11 1.071 <1.25 Reserved Supported CL Settings 9,11.12,13,14,15,16 nCK Supported CL Settings with read DBI 11,13,14,15,16,18,19 nCK Supported CWL Settings 9,10,11,12,14 nCK - 34 - Rev. 1.91 datasheet Registered DIMM DDR4 SDRAM [ Table 25 ] DDR4-2400 Speed Bins and Operations Speed Bin DDR4-2400 CL-nRCD-nRP 17-17-17 Parameter Symbol Internal read command to first data tAA Internal read command to first data with read DBI enabled tAA_DBI ACT to internal read or write delay time tRCD PRE command period tRP ACT to PRE command period tRAS ACT to ACT or REF command period CWL = 9 CWL = 9,11 CWL = 10,12 CWL = 11,14 CWL = 12,16 Normal Read DBI CL = 9 CL = 11 tRC CL = 12 tCK(AVG) CL = 10 CL = 12 tCK(AVG) CL = 11 CL = 13 tCK(AVG) CL = 12 CL = 14 tCK(AVG) CL = 12 CL = 14 tCK(AVG) CL = 13 CL = 15 tCK(AVG) CL = 14 CL = 16 tCK(AVG) CL = 14 CL = 17 tCK(AVG) CL = 15 CL = 18 tCK(AVG) CL = 16 CL = 19 tCK(AVG) CL = 15 CL = 18 tCK(AVG) CL = 16 CL = 19 tCK(AVG) NOTE 18.00 ns 11 tAA(max) + 3nCK ns 11 - ns 11 - ns 11 9 x tREFI ns 11 - ns 11 ns 1,2,3,4,9 min max 14.16 (13.75)5,11 tAA(min) + 3nCK 14.16 (13.75)5,11 14.16 (13.75)5,11 32 46.16 (45.75)5,11 tCK(AVG) CL = 10 Unit Reserved 1.5 1.6 ns 1,2,3,4,9 ns 4 ns 1,2,3,4,8 <1.5 ns 1,2,3,8 ns 4 <1.25 ns 1,2,3,4,8 Reserved 1.25 <1.5 5,11 (Optional) 1.25 Reserved 1.071 (Optional)5,11 1.071 <1.25 ns 1,2,3,8 ns 4 <1.071 ns 1,2,3,4,8 <1.071 ns 1,2,3,8 Reserved ns 1,2,3,4 Reserved ns 1,2,3,4 ns 1,2,3 12,13 Reserved 0.937 (Optional)5,11 0.937 CL = 17 CL = 20 tCK(AVG) 0.833 <0.937 CL = 18 CL = 21 tCK(AVG) 0.833 <0.937 Supported CL Settings 10,11,12,13,14,15,16,17,18 nCK Supported CL Settings with read DBI 12,13,14,15,16,18,19,20,21 nCK Supported CWL Settings 9,10,11,12,14,16 nCK - 35 - Rev. 1.91 datasheet Registered DIMM DDR4 SDRAM [ Table 26 ] DDR4-2666 Speed Bins and Operations Speed Bin DDR4-2666 CL-nRCD-nRP 19-19-19 Parameter Symbol Internal read command to first data tAA Internal read command to first data with read DBI enabled tAA_DBI ACT to internal read or write delay time tRCD PRE command period tRP ACT to PRE command period tRAS ACT to ACT or REF command period tRC Normal CWL = 9 CWL = 9,11 CWL = 10,12 CWL = 11,14 CWL = 12,16 CWL = 14.18 Unit NOTE 18.00 ns 11 tAA(max) + 3nCK ns 11 - ns 11 - ns 11 9 x tREFI ns 11 - ns 11 ns 1,2,3,4,10 ns 1,2,3,10 ns 4 ns 1,2,3,4,9 ns 1,2,3,9 ns 4 ns 1,2,3,4,9 ns 1,2,3,9 ns 4 ns 1,2,3,4,9 min max 14.2514 (13.75)5,12 tAA(min) + 3nCK 14.25 (13.75)5,12 14.2514 (13.75)5,12 32 46.25 (45.75)5,12 Read DBI CL = 9 CL = 11 tCK(AVG) CL = 10 CL = 12 tCK(AVG) CL = 10 CL = 12 tCK(AVG) CL = 11 CL = 13 tCK(AVG) CL = 12 CL = 14 tCK(AVG) CL = 12 CL = 14 tCK(AVG) CL = 13 CL = 15 tCK(AVG) CL = 14 CL = 16 tCK(AVG) CL = 14 CL = 17 tCK(AVG) Reserved 1.5 1.6 Reserved 1.25 <1.5 (Optional)5,12 1.25 <1.5 Reserved 1.071 <1.25 (Optional)5,12 1.071 <1.25 Reserved 0.937 <1.071 CL = 15 CL = 18 tCK(AVG) CL = 16 CL = 19 tCK(AVG) ns 1,2,3,9 CL = 15 CL = 18 tCK(AVG) Reserved ns 4 CL = 16 CL = 19 tCK(AVG) Reserved ns 1,2,3,4,9 CL = 17 CL = 20 tCK(AVG) CL = 18 CL = 21 tCK(AVG) CL = 17 CL = 20 tCK(AVG) CL = 18 CL = 21 tCK(AVG) CL = 19 CL = 22 tCK(AVG) 0.75 <0.833 CL = 20 CL = 23 tCK(AVG) 0.75 <0.833 (Optional)5,12 0.937 <1.071 0.833 <0.937 (Optional) 5,12 0.833 <0.937 Reserved Reserved ns 1,2,3,4,9 ns 1,2,3 ns 1,2,3,4 ns 1,2,3,4 ns 1,2,3,4 ns 1,2,3 12 Supported CL Settings 10,11,12,13,14,15,16,17,18,19,20 nCK Supported CL Settings with read DBI 12,13,14,15,17,18,19,20,21,22,23 nCK Supported CWL Settings 9,10,11,12,14,16,18 nCK - 36 - 1,2,3,4,9 Registered DIMM datasheet Rev. 1.91 DDR4 SDRAM 16.2 Speed Bin Table Note Absolute Specification - VDDQ = VDD = 1.20V +/- 0.06 V - VPP = 2.5V +0.25/-0.125 V - The values defined with above-mentioned table are DLL ON case. - DDR4-1600, 1866, 2133,2400 and 2666 Speed Bin Tables are valid only when Geardown Mode is disabled. 1. The CL setting and CWL setting result in tCK(avg).MIN and tCK(avg).MAX requirements. When making a selection of tCK(avg), both need to be fulfilled: Requirements from CL setting as well as requirements from CWL setting. 2. tCK(avg).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchronized by the DLL - all possible intermediate frequencies may not be guaranteed. CL in clock cycle is calculated from tAA following rounding algorithm defined in Section 13.5. 3. tCK(avg).MAX limits: Calculate tCK(avg) = tAA.MAX / CL SELECTED and round the resulting tCK(avg) down to the next valid speed bin (i.e. 1.5ns or 1.25ns or 1.071ns or 0.937ns or 0.833ns). This result is tCK(avg).MAX corresponding to CL SELECTED. 4. `Reserved' settings are not allowed. User must program a different value. 5. 'Optional' settings allow certain devices in the industry to support this setting, however, it is not a mandatory feature. Refer to supplier's data sheet and/or the DIMM SPD information if and how this setting is supported. 6. Any DDR4-1866 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/ Characterization. 7. Any DDR4-2133 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/ Characterization. 8. Any DDR4-2400 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/ Characterization. 9. Any DDR4-2666 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/ Characterization. 10. DDR4-1600 AC timing apply if DRAM operates at lower than 1600 MT/s data rate. 11. Parameters apply from tCK(avg) min to tCK(avg) max at all standard JEDEC clock period values as stated in the Speed Bin Tables. 12. CL number in parentheses, it means that these numbers are optional. 13. DDR4 SDRAM supports CL=9 as long as a system meets tAA(min). 14. Each speed bin lists the timing requirements that need to be supported in order for a given DRAM to be JEDEC compliant. JEDEC compliance does not require support for all speed bins within a given speed. JEDEC compliance requires meeting the parameters for a least one of the listed speed bins. - 37 - Rev. 1.91 datasheet Registered DIMM DDR4 SDRAM 17. Timing Parameters by Speed Grade [ Table 27 ] Timing Parameters by Speed Bin for DDR4-1600 to DDR4-2666 Speed DDR4-1600 DDR4-1866 DDR4-2133 DDR4-2400 DDR4-2666 Parameter Symbol MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX Minimum Clock Cycle Time (DLL off mode) tCK (DLL_OFF) 8 20 8 20 8 20 8 20 8 20 Units NOTE Clock Timing ns Average Clock Period tCK(avg) 1.25 <1.5 1.071 <1.25 0.937 <1.071 0.833 <0.937 0.750 <0.833 ns Average high pulse width tCH(avg) 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 tCK(avg) Average low pulse width tCL(avg) 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 tCK(avg) tCK(avg)min + tJIT(per)min_tot tCK(avg)m ax + tJIT(per)max_tot 35,36 Absolute Clock Period tCK(abs) Absolute clock HIGH pulse width tCH(abs) 0.45 - 0.45 - 0.45 - 0.45 - 0.45 - tCK(avg) 23 Absolute clock LOW pulse width tCL(abs) 0.45 - 0.45 - 0.45 - 0.45 - 0.45 - tCK(avg) 24 Clock Period Jitter- total JIT(per)_tot -63 63 -54 54 -47 47 -42 42 -38 38 ps 23 Clock Period Jitter- deterministic JIT(per)_dj -31 31 -27 27 -23 23 -21 21 -19 19 ps 26 tJIT(per, lck) -50 50 -43 43 -38 38 -33 33 -30 30 ps tJIT(cc) - 125 - 107 - 94 - 83 - 75 ps ps Clock Period Jitter during DLL locking period Cycle to Cycle Period Jitter Cycle to Cycle Period Jitter during DLL locking period tCK(avg) tJIT(cc, lck) - 100 - 86 - 75 - 67 - 60 tJIT(duty) TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD ps Cumulative error across 2 cycles tERR(2per) -92 92 -79 79 -69 69 -61 61 -55 55 ps Cumulative error across 3 cycles tERR(3per) -109 109 -94 94 -82 82 -73 73 -66 66 ps Cumulative error across 4 cycles tERR(4per) -121 121 -104 104 -91 91 -81 81 -73 73 ps Cumulative error across 5 cycles tERR(5per) -131 131 -112 112 -98 98 -87 87 -78 78 ps Cumulative error across 6 cycles tERR(6per) -139 139 -119 119 -104 104 -92 92 -83 83 ps Cumulative error across 7 cycles tERR(7per) -145 145 -124 124 -109 109 -97 97 -87 87 ps Cumulative error across 8 cycles tERR(8per) -151 151 -129 129 -113 113 -101 101 -91 91 ps Duty Cycle Jitter Cumulative error across 9 cycles tERR(9per) -156 156 -134 134 -117 117 -104 104 -94 94 ps Cumulative error across 10 cycles tERR(10per) -160 160 -137 137 -120 120 -107 107 -96 96 ps Cumulative error across 11 cycles tERR(11per) -164 164 -141 141 -123 123 -110 110 -99 99 ps Cumulative error across 12 cycles tERR(12per) -168 168 -144 144 -126 126 -112 112 -101 101 ps Cumulative error across 13 cycles tERR(13per) -172 172 -147 147 -129 129 -114 114 -103 103 ps Cumulative error across 14 cycles tERR(14per) -175 175 -150 150 -131 131 -116 116 -104 104 ps Cumulative error across 15 cycles tERR(15per) -178 178 -152 152 -133 133 -118 118 -106 106 ps Cumulative error across 16 cycles tERR(16per) -180 189 -155 155 -135 135 -120 120 -108 108 ps Cumulative error across 17 cycles tERR(17per) -183 183 -157 157 -137 137 -122 122 -110 110 ps Cumulative error across 18 cycles tERR(18per) -185 185 -159 159 -139 139 -124 124 -112 112 ps t ERR(nper)min = ((1 + 0.68ln(n)) * tJIT(per)_total min) tERR(nper)max = ((1 + 0.68ln(n)) * tJIT(per)_total max) Cumulative error across n = 13, 14 . . . 49, 50 cycles tERR(nper) Command and Address setup time to CK_t, CK_c referenced to Vih(ac) / Vil(ac) levels tIS(base) 115 - 100 - 80 - 62 - TBD - ps Command and Address setup time to CK_t,CK_c referenced to Vref levels tIS(Vref) 215 - 200 - 180 - 162 - TBD - ps Command and Address hold time to CK_t, CK_c referenced to Vih(dc) / Vil(dc) levels tIH(base) 140 - 125 - 105 - 87 - TBD - ps Command and Address hold time to CK_t, CK_c referenced to Vref levels tIH(Vref) 215 - 200 - 180 - 162 - TBD - ps Control and Address Input pulse width for each input tIPW 600 - 525 - 460 - 410 - 385 - ps CAS_n to CAS_n command delay for same bank group tCCD_L max(5 nCK, 6.250 ns) - max(5 nCK, 5.355 ns) - max(5 nCK, 5.625 ns) - max(5 nCK, 5 ns) - max(5 nCK, 5 ns) - nCK 34 CAS_n to CAS_n command delay for different bank group tCCD_S 4 - 4 - 4 - 4 - 4 - nCK 34 ACTIVATE to ACTIVATE Command delay to different bank group for 2KB page size tRRD_S(2K) Max(4nC K,6ns) - Max(4nC K,5.3ns) - Max(4nC K,5.3ns) - Max(4nC K,5.3ns) - Max(4nC K,5.3ns) - nCK 34 ACTIVATE to ACTIVATE Command delay to different bank group for 2KB page size tRRD_S(1K) Max(4nC K,5ns) Max(4nC K,3.3ns) - Max(4nC K,3ns) - nCK 34 ps Command and Address Timing Max(4nC K,4.2ns) Max(4nC K,3.7ns) - 38 - Rev. 1.91 datasheet Registered DIMM Speed DDR4-1600 DDR4-1866 DDR4 SDRAM DDR4-2133 DDR4-2400 DDR4-2666 Units NOTE - nCK 34 Max(4nC K,6.4ns) - nCK 34 - Max(4nC K,4.9ns) - nCK 34 Max(4nC K,4.9ns) - Max(4nC K,4.9ns) - nCK 34 Max(28nC K,30ns) Max(28nC K,30ns) - Max(28nC K,30ns) - ns 34 Max(20nC K,23ns) Max(20nC K,21ns) Max(20nC K,21ns) - Max(20nC K,21ns) - ns 34 Max(16nC K,17ns) Max(16nC K,15ns) Max(16nC K,13ns) - Max(16nC K,12ns) - ns 34 - max (2nCK, 2.5ns) - max (2nCK, 2.5ns) - ns 1,2,e,3 4 max(4nC K,7.5ns) - max (4nCK,7.5 ns) - max (4nCK,7.5 ns) - 1,34 max(4nC K,7.5ns) - max (4nCK,7.5 ns) - max (4nCK,7.5 ns) - 34 - 15 - 15 - 15 - ns 1 - tWR+max (5nCK,3.7 5ns) - tWR+max (5nCK,3.7 5ns) - tWR+max (5nCK,3.7 5ns) - ns 1, 28 tWTR_S+ max (5nCK,3.7 5ns) - tWTR_S+ max (5nCK,3.7 5ns) - tWTR_S+ max (5nCK,3.7 5ns) - tWTR_S+ max (5nCK,3.7 5ns) - ns 2, 29, 34 - tWTR_L+ max (5nCK,3.7 5ns) - tWTR_L+ max (5nCK,3.7 5ns) - tWTR_L+ max (5nCK,3.7 5ns) - tWTR_L+ max (5nCK,3.7 5ns) - ns 3,30, 34 597 - 597 - 768 - 768 - 854 - nCK 8 - 8 - 8 - 8 - 8 - nCK max(24nC K,15ns) - max(24nC K,15ns) - max(24nC K,15ns) - max(24nC K,15ns) - max(24nC K,15ns) - nCK 50 tMPRR 1 - 1 - 1 - 1 - 1 - nCK 33 Multi Purpose Register Write Recovery Time tWR_MPR tMOD (min) + AL + PL - tMOD (min) + AL + PL - tMOD (min) + AL + PL - tMOD (min) + AL + PL - tMOD (min) + AL + PL - nCK Auto precharge write recovery + precharge time tDAL(min) DQ0 or DQL0 driven to 0 set-up time to first DQS rising edge tPDA_S 0.5 - 0.5 - 0.5 - 0.5 - 0.5 - UI 45,47 DQ0 or DQL0 driven to 0 hold time from last DQS falling edge tPDA_H 0.5 - 0.5 - 0.5 - 0.5 - 0.5 - UI 46,47 tCAL max(3 nCK, 3.748 ns) - max(3 nCK, 3.748 ns) - max(3 nCK, 3.748 ns) - max(3 nCK, 3.748 ns) - max(3 nCK, 3.748 ns) - nCK Mode Register Set command cycle time in CAL mode tMRD_tCAL tMOD+ tCAL - tMOD+ tCAL - tMOD+ tCAL - tMOD+ tCAL - tMOD+ tCAL - nCK Mode Register Set update delay in CAL mode tMOD_tCAL tMOD+ tCAL - tMOD+ tCAL - tMOD+ tCAL - tMOD+ tCAL - tMOD+ tCAL - nCK DQS_t,DQS_c to DQ skew, per group, per access tDQSQ - 0.16 - 0.16 - 0.16 - 0.17 - 0.18 tCK(avg)/ 2 13,18,3 9,49 DQ output hold time per group, per access from DQS_t,DQS_c tQH 0.76 - 0.76 - 0.76 - 0.74 - 0.74 - tCK(avg)/ 2 13,17,1 8,39,49 Data Valid Window per device per UI: (tQH - tDQSQ) of each UI on a given DRAM tDVWd 0.63 - 0.63 - 0.64 - 0.64 - TBD - UI 17,18,3 9,49 Data Valid Window, per pin per UI: (tQH tDQSQ) each UI on a pin of a given DRAM tDVWp 0.66 - 0.66 - 0.69 - 0.72 - 0.72 - UI 17,18,3 9,49 DQ low impedance time from CK_t, CK_c tLZ(DQ) -450 225 -390 195 -390 180 -330 175 -310 170 ps 39 DQ high impedance time from CK_t, CK_c tHZ(DQ) - 225 - 195 - 180 - 175 - 170 ps 39 tRPRE 0.9 NOTE44 0.9 NOTE44 0.9 NOTE44 0.9 NOTE 44 0.9 NOTE 44 tCK 39,40 Parameter Symbol MIN MAX MIN ACTIVATE to ACTIVATE Command delay to different bank group for 1/2KB page size tRRD_S(1/2K) Max(4nC K,5ns) Max(4nC K,4.2ns) ACTIVATE to ACTIVATE Command delay to same bank group for 2KB page size tRRD_L(2K) Max(4nC K,7.5ns) ACTIVATE to ACTIVATE Command delay to same bank group for 1KB page size tRRD_L(1K) ACTIVATE to ACTIVATE Command delay to same bank group for 1/2KB page size MAX MIN MAX MIN MAX MIN MAX Max(4nC K,3.7ns) Max(4nC K,3.3ns) - Max(4nC K,3ns) Max(4nC K,6.4ns) Max(4nC K,6.4ns) Max(4nC K,6.4ns) - Max(4nC K,6ns) Max(4nC K,5.3ns) Max(4nC K,5.3ns) Max(4nC K,4.9ns) tRRD_L(1/2K) Max(4nC K,6ns) Max(4nC K,5.3ns) Max(4nC K,5.3ns) Four activate window for 2KB page size tFAW_2K Max(28nC K,35ns) Max(28nC K,30ns) Four activate window for 1KB page size tFAW_1K Max(20nC K,25ns) Four activate window for 1/2KB page size tFAW_1/2K Max(16nC K,20ns) Delay from start of internal write transaction to internal read command for different bank group tWTR_S max(2nC K,2.5ns) - max(2nC K,2.5ns) - max(2nC K,2.5ns) Delay from start of internal write transaction to internal read command for same bank group tWTR_L max(4nC K,7.5ns) - max(4nC K,7.5ns) - Internal READ Command to PRECHARGE Command delay tRTP max(4nC K,7.5ns) - max(4nC K,7.5ns) - WRITE recovery time tWR 15 - 15 Write recovery time when CRC and DM are enabled tWR_CRC _DM tWR+max (4nCK,3.7 5ns) - tWR+max (5nCK,3.7 5ns) delay from start of internal write transaction to internal read command for different bank group with both CRC and DM enabled tWTR_S_C RC_DM tWTR_S+ max (4nCK,3.7 5ns) - delay from start of internal write transaction to internal read command for same bank group with both CRC and DM enabled tWTR_L_C RC_DM tWTR_L+ max (4nCK,3.7 5ns) DLL locking time tDLLK Mode Register Set command cycle time tMRD Mode Register Set command update delay tMOD Multi-Purpose Register Recovery Time Programmed WR + roundup (tRP / tCK(avg)) nCK CS_n to Command Address Latency CS_n to Command Address Latency DRAM Data Timing Data Strobe Timing DQS_t, DQS_c differential READ Pre-amble (1 clock preamble) - 39 - Rev. 1.91 datasheet Registered DIMM Speed DDR4-1600 DDR4-1866 DDR4 SDRAM DDR4-2133 DDR4-2400 DDR4-2666 Units NOTE NOTE 44 tCK 39,41 NOTE 45 tCK 39 Parameter Symbol MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX DQS_t, DQS_c differential READ Preamble (2 clock preamble) tRPRE2 NA NA NA NA NA NA 1.8 NOTE 44 1.8 DQS_t, DQS_c differential READ Postamble tRPST 0.33 NOTE 45 0.33 NOTE 45 0.33 NOTE 45 0.33 NOTE 45 0.33 DQS_t,DQS_c differential output high time tQSH 0.4 - 0.4 - 0.4 - 0.4 - 0.4 - tCK 21,39 DQS_t,DQS_c differential output low time tQSL 0.4 - 0.4 - 0.4 - 0.4 - 0.4 - tCK 20,39 DQS_t, DQS_c differential WRITE Preamble (1 clock preamble) tWPRE 0.9 - 0.9 - 0.9 - 0.9 - 0.9 - tCK 42 DQS_t, DQS_c differential WRITE Preamble (2 clock preamble) tWPRE2 NA 1.8 - 1.8 - tCK 43 tWPST 0.33 - 0.33 - 0.33 - 0.33 - 0.33 - tCK DQS_t and DQS_c low-impedance time (Referenced from RL-1) tLZ(DQS) -450 225 -390 195 -360 180 -330 175 -310 170 ps 39 DQS_t and DQS_c high-impedance time (Referenced from RL+BL/2) tHZ(DQS) - 225 - 195 - 180 - 175 - 170 ps 39 DQS_t, DQS_c differential input low pulse width tDQSL 0.46 0.54 0.46 0.54 0.46 0.54 0.46 0.54 0.46 0.54 tCK DQS_t, DQS_c differential input high pulse width tDQSH 0.46 0.54 0.46 0.54 0.46 0.54 0.46 0.54 0.46 0.54 tCK DQS_t, DQS_c rising edge to CK_t, CK_c rising edge (1 clock preamble) tDQSS -0.27 0.27 -0.27 0.27 -0.27 0.27 -0.27 0.27 -0.27 0.27 tCK 42 DQS_t, DQS_c rising edge to CK_t, CK_c rising edge (2 clock preamble) tDQSS2 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD tCK 43 DQS_t, DQS_c falling edge setup time to CK_t, CK_c rising edge tDSS 0.18 - 0.18 - 0.18 - 0.18 - 0.18 - tCK DQS_t, DQS_c falling edge hold time from CK_t, CK_c rising edge tDSH 0.18 - 0.18 - 0.18 - 0.18 - 0.18 - tCK DQS_t, DQS_c rising edge output timing locatino from rising CK_t, CK_c with DLL On mode tDQSCK (DLL On) -225 225 -195 195 -180 180 -175 175 -170 170 ps 37,38,3 9 DQS_t, DQS_c rising edge output variance window per DRAM tDQSCKI (DLL On) 270 ps 37,38,3 9 DQS_t, DQS_c differential WRITE Postamble NA 370 NA 330 310 290 MPSM Timing Command path disable delay upon MPSM entry tMPED tMOD(min )+ tCPDED(min) - tMOD(min )+ tCPDED(min) - tMOD(min )+ tCPDED(min) - tMOD(min )+ tCPDED(min) - TBD - Valid clock requirement after MPSM entry tCKMPE tMOD(min )+ tCPDED(min) - tMOD(min ) + tCPDED(min) - tMOD(min )+ tCPDED(min) - tMOD(min )+ tCPDED(min) - TBD - Valid clock requirement before MPSM exit tCKMPX tCKSRX( min) - tCKSRX( min) - tCKSRX( min) - tCKSRX( min) - TBD - tXMP tXS(min) - tXS(min) - tXS(min) - tXS(min) - TBD - Exit MPSM to commands requiring a locked DLL tXMPDLL tXMP(min )+ tXSDLL(min) - tXMP(min )+ tXSDLL(min) - tXMP(min )+ tXSDLL(min) - tXMP(min )+ tXSDLL(min) - TBD - CS setup time to CKE tMPX_S tIS(min) + tIHL(min) - tIS(min) + tIHL(min) - tIS(min) + tIHL(min) - tIS(min) + tIHL(min) - TBD - Power-up and RESET calibration time tZQinit 1024 - 1024 - 1024 - 1024 - 1024 - nCK Normal operation Full calibration time tZQoper 512 - 512 - 512 - 512 - 512 - nCK tZQCS 128 - 128 - 128 - 128 - 128 - nCK Exit Reset from CKE HIGH to a valid command tXPR max (5nCK,tR FC(min)+ 10ns) - max (5nCK,tR FC(min)+ 10ns) - max (5nCK,tR FC(min)+ 10ns) - max (5nCK,tR FC(min)+ 10ns) - max (5nCK,tR FC(min)+ 10ns) - nCK Exit Self Refresh to commands not requiring a locked DLL tXS tRFC(min) +10ns - tRFC(min) +10ns - tRFC(min) +10ns - tRFC(min) +10ns - tRFC(min) +10ns - nCK SRX to commands not requiring a locked DLL in Self Refresh ABORT tXS_ABORT(mi n) tRFC4(mi n)+10ns - tRFC4(mi n)+10ns - tRFC4(mi n)+10ns - tRFC4(mi n)+10ns - tRFC4(mi n)+10ns - nCK Exit Self Refresh to ZQCL,ZQCS and MRS (CL,CWL,WR,RTP and Gear Down) tXS_FAST (min) tRFC4(mi n)+10ns - tRFC4(mi n)+10ns - tRFC4(mi n)+10ns - tRFC4(mi n)+10ns - tRFC4(mi n)+10ns - nCK Exit Self Refresh to commands requiring a locked DLL tXSDLL tDLLK(mi n) - tDLLK(mi n) - tDLLK(mi n) - tDLLK(mi n) - tDLLK(mi n) - nCK Minimum CKE low width for Self refresh entry to exit timing tCKESR tCKE(min) +1nCK - tCKE(min) +1nCK - tCKE(min) +1nCK - tCKE(min) +1nCK - tCKE(min) +1nCK - nCK Exit MPSM to commands not requiring a locked DLL Calibration Timing Normal operation Short calibration time Reset/Self Refresh Timing - 40 - Rev. 1.91 datasheet Registered DIMM Speed DDR4-1600 DDR4-1866 DDR4 SDRAM DDR4-2133 DDR4-2400 DDR4-2666 Units Parameter Symbol MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX Minimum CKE low width for Self refresh entry to exit timing with CA Parity enabled tCKESR_ PAR tCKE(min) + 1nCK+PL - tCKE(min) + 1nCK+PL - tCKE(min) + 1nCK+PL - tCKE(min) + 1nCK+PL - tCKE(min) + 1nCK+PL - nCK Valid Clock Requirement after Self Refresh Entry (SRE) or Power-Down Entry (PDE) tCKSRE max(5nC K,10ns) - max(5nC K,10ns) - max(5nC K,10ns) - max (5nCK,10 ns) - max (5nCK,10 ns) - nCK Valid Clock Requirement after Self Refresh Entry (SRE) or Power-Down when CA Parity is enabled tCKSRE_PAR max (5nCK,10 ns)+PL - max (5nCK,10 ns)+PL - max (5nCK,10 ns)+PL - max (5nCK,10 ns)+PL - max (5nCK,10 ns)+PL - nCK tCKSRX max(5nC K,10ns) - max(5nC K,10ns) - max(5nC K,10ns) - max (5nCK,10 ns) - max (5nCK,10 ns) - nCK tXP max (4nCK,6n s) - max (4nCK,6n s) - max (4nCK,6n s) - max (4nCK,6n s) - max (4nCK,6n s) - nCK tCKE max (3nCK, 5ns) - max (3nCK, 5ns) - max (3nCK, 5ns) - max (3nCK, 5ns) - max (3nCK, 5ns) - nCK Valid Clock Requirement before Self Refresh Exit (SRX) or Power-Down Exit (PDX) or Reset Exit NOTE Power Down Timing Exit Power Down with DLL on to any valid command; Exit Precharge Power Down with DLL frozen to commands not requiring a locked DLL CKE minimum pulse width Command pass disable delay 31,32 tCPDED 4 - 4 - 4 - 4 - 4 - nCK tPD tCKE(min) 9*tREFI tCKE(min) 9*tREFI tCKE(min) 9*tREFI tCKE(min) 9*tREFI tCKE(min) 9*tREFI nCK 6 tACTPDEN 1 - 1 - 2 - 2 - 2 - nCK 7 Timing of PRE or PREA command to Power Down entry tPRPDEN 1 - 1 - 2 - 2 - 2 - nCK 7 Timing of RD/RDA command to Power Down entry tRDPDEN RL+4+1 - RL+4+1 - RL+4+1 - RL+4+1 - RL+4+1 - nCK Timing of WR command to Power Down entry (BL8OTF, BL8MRS, BC4OTF) tWRPDEN WL+4+(t WR/ tCK(avg)) - WL+4+(t WR/ tCK(avg)) - WL+4+(t WR/ tCK(avg)) - WL+4+(t WR/ tCK(avg)) - WL+4+(t WR/ tCK(avg)) - nCK 4 tWRAPDEN WL+4+W R+1 - WL+4+W R+1 - WL+4+W R+1 - WL+4+W R+1 - WL+4+W R+1 - nCK 5 Timing of WR command to Power Down entry (BC4MRS) tWRPBC4DEN WL+2+(t WR/ tCK(avg)) - WL+2+(t WR/ tCK(avg)) - WL+2+(t WR/ tCK(avg)) - WL+2+(t WR/ tCK(avg)) - WL+2+(t WR/ tCK(avg)) - nCK 4 Timing of WRA command to Power Down entry (BC4MRS) tWRAPBC4DEN WL+2+W R+1 - WL+2+W R+1 - WL+2+W R+1 - WL+2+W R+1 - WL+2+W R+1 - nCK 5 Timing of REF command to Power Down entry tREFPDEN 1 - 1 - 2 - 2 - 2 - nCK 7 Timing of MRS command to Power Down entry tMRSPDEN tMOD(min ) - tMOD(min ) - tMOD(min ) - tMOD(min ) - tMOD(min ) - nCK Mode Register Set command cycle time in PDA mode tMRD_PDA max(16nC K,10ns) - max(16nC K,10ns) - max(16nC K,10ns) - max(16nC K,10ns) - max(16nC K,10ns) - nCK Mode Register Set command update delay in PDA mode tMOD_PDA Power Down Entry to Exit Timing Timing of ACT command to Power Down entry Timing of WRA command to Power Down entry (BL8OTF, BL8MRS, BC4OTF) PDA Timing tMOD tMOD tMOD tMOD tMOD nCK ODT Timing Asynchronous RTT turn-on delay (PowerDown with DLL frozen) tAONAS 1.0 9.0 1.0 9.0 1.0 9.0 1.0 9.0 1.0 9.0 ns Asynchronous RTT turn-off delay (PowerDown with DLL frozen) tAOFAS 1.0 9.0 1.0 9.0 1.0 9.0 1.0 9.0 1.0 9.0 ns tADC 0.3 0.7 0.3 0.7 0.3 0.7 0.3 0.7 0.3 0.7 tCK(avg) tWLMRD 40 - 40 - 40 - 40 - 40 - nCK 12 tWLDQSEN 25 - 25 - 25 - 25 - 25 - nCK 12 Write leveling setup time from rising CK_t, CK_c crossing to rising DQS_t/DQS_n crossing tWLS 0.13 - 0.13 - 0.13 - 0.13 - 0.13 - tCK(avg) Write leveling hold time from rising DQS_t/ DQS_n crossing to rising CK_t, CK_ crossing tWLH 0.13 - 0.13 - 0.13 - 0.13 - 0.13 - tCK(avg) RTT dynamic change skew Write Leveling Timing First DQS_t/DQS_n rising edge after write leveling mode is programmed DQS_t/DQS_n delay after write leveling mode is programmed Write leveling output delay tWLO 0 9.5 0 9.5 0 9.5 0 9.5 0 9.5 ns Write leveling output error tWLOE 0 2 0 2 0 2 0 2 0 2 ns Commands not guaranteed to be executed during this time tPAR_UNKNOWN - PL - PL - PL - PL - PL nCK Delay from errant command to ALERT_n assertion tPAR_ALERT _ON - PL+6ns - PL+6ns - PL+6ns - PL+6ns - PL+6ns nCK CA Parity Timing - 41 - datasheet Registered DIMM Speed Parameter Rev. 1.91 DDR4-1600 DDR4-1866 DDR4 SDRAM DDR4-2133 DDR4-2400 DDR4-2666 Units Symbol MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX Pulse width of ALERT_n signal when asserted tPAR_ALERT _PW 48 96 56 112 64 128 72 144 80 160 nCK Time from when Alert is asserted till controller must start providing DES commands in Persistent CA parity mode tPAR_ALERT _RSP - 43 - 50 - 57 - 64 71 nCK Parity Latency PL 4 4 4 5 5 NOTE nCK CRC Error Reporting CRC error to ALERT_n latency tCRC_ALERT 3 13 3 13 3 13 3 13 3 13 ns CRC ALERT_n pulse width CRC_ALERT_ PW 6 10 6 10 6 10 6 10 6 10 nCK Exit RESET from CKE HIGH to a valid MRS geardown (T2/Reset) tXPR_GEAR - - - - - - - - TBD CKE High Assert to Gear Down Enable time(T2/CKE) tXS_GEAR - - - - - - - - TBD MRS command to Sync pulse time(T3) tSYNC_GEA R - - - - - - - - Sync pulse to First valid command(T4) tCMD_GEAR - - - - - - - - Geardown setup time tGEAR_setup - - - - - - - - 2 - nCK Geardown hold time tGEAR_hold - - - - - - - - 2 - nCK Geardown timing TBD - 27 TBD 27 tREFI tRFC1 (min) tRFC2 (min) tRFC4 (min) 2Gb 160 - 160 - 160 - 160 - 160 - ns 34 4Gb 260 - 260 - 260 - 260 - 260 - ns 34 8Gb 350 - 350 - 350 - 350 - 350 - ns 34 16Gb 550 - 550 - 550 - 550 - 550 - ns 34 2Gb 110 - 110 - 110 - 110 - 110 - ns 34 4Gb 160 - 160 - 160 - 160 - 160 - ns 34 8Gb 260 - 260 - 260 - 260 - 260 - ns 34 16Gb 350 - 350 - 350 - 350 - 350 - ns 34 2Gb 90 - 90 - 90 - 90 - 90 - ns 34 4Gb 110 - 110 - 110 - 110 - 110 - ns 34 8Gb 160 - 160 - 160 - 160 - 160 - ns 34 16Gb 260 - 260 - 260 - 260 - 260 - ns 34 - 42 - Registered DIMM datasheet Rev. 1.91 DDR4 SDRAM NOTE : 1. Start of internal write transaction is defined as follows : For BL8 (Fixed by MRS and on-the-fly) : Rising clock edge 4 clock cycles after WL. For BC4 (on-the-fly) : Rising clock edge 4 clock cycles after WL. For BC4 (fixed by MRS) : Rising clock edge 2 clock cycles after WL. 2. A separate timing parameter will cover the delay from write to read when CRC and DM are simultaneously enabled 3. Commands requiring a locked DLL are: READ (and RAP) and synchronous ODT commands. 4. tWR is defined in ns, for calculation of tWRPDEN it is necessary to round up tWR/tCK following rounding algorithm defined in "13.5 Rounding Algorithms". 5. WR in clock cycles as programmed in MR0. 6. tREFI depends on TOPER. 7. CKE is allowed to be registered low while operations such as row activation, precharge, autoprecharge or refresh are in progress, but power-down IDD spec will not be applied until finishing those operations. 8. For these parameters, the DDR4 SDRAM device supports tnPARAM[nCK]=RU{tPARAM[ns]/tCK(avg)[ns]}, which is in clock cycles assuming all input clock jitter specifications are satisfied 9. When CRC and DM are both enabled, tWR_CRC_DM is used in place of tWR. 10. When CRC and DM are both enabled tWTR_S_CRC_DM is used in place of tWTR_S. 11. When CRC and DM are both enabled tWTR_L_CRC_DM is used in place of tWTR_L. 12. The max values are system dependent. 13. DQ to DQS total timing per group where the total includes the sum of deterministic and random timing terms for a specified BER. BER spec and measurement method are tbd. 14. The deterministic component of the total timing. Measurement method tbd. 15. DQ to DQ static offset relative to strobe per group. Measurement method tbd. 16. This parameter will be characterized and guaranteed by design. 17. When the device is operated with the input clock jitter, this parameter needs to be derated by the actual tjit(per)_total of the input clock. (output deratings are relative to the SDRAM input clock). Example tbd. 18. DRAM DBI mode is off. 19. DRAM DBI mode is enabled. Applicable to x8 and x16 DRAM only. 20. tQSL describes the instantaneous differential output low pulse width on DQS_t - DQS_c, as measured from on falling edge to the next consecutive rising edge 21. tQSH describes the instantaneous differential output high pulse width on DQS_t - DQS_c, as measured from on falling edge to the next consecutive rising edge 22. There is no maximum cycle time limit besides the need to satisfy the refresh interval tREFI 23. tCH(abs) is the absolute instantaneous clock high pulse width, as measured from one rising edge to the following falling edge 24. tCL(abs) is the absolute instantaneous clock low pulse width, as measured from one falling edge to the following rising edge 25. Total jitter includes the sum of deterministic and random jitter terms for a specified BER. BER target and measurement method are tbd. 26. The deterministic jitter component out of the total jitter. This parameter is characterized and gauranteed by design. 27. This parameter has to be even number of clocks 28. When CRC and DM are both enabled, tWR_CRC_DM is used in place of tWR. 29. When CRC and DM are both enabled tWTR_S_CRC_DM is used in place of tWTR_S. 30. When CRC and DM are both enabled tWTR_L_CRC_DM is used in place of tWTR_L. 31. After CKE is registered LOW, CKE signal level shall be maintained below VILDC for tCKE specification (Low pulse width). 32. After CKE is registered HIGH, CKE signal level shall be maintained above VIHDC for tCKE specification (HIGH pulse width). 33. Defined between end of MPR read burst and MRS which reloads MPR or disables MPR function. 34. Parameters apply from tCK(avg)min to tCK(avg)max at all standard JEDEC clock period values as stated in the Speed Bin Tables. 35. This parameter must keep consistency with Speed-Bin Tables shown in section 10. 36. DDR4-1600 AC timing apply if DRAM operates at lower than 1600 MT/s data rate. UI=tCK(avg).min/2 37. applied when DRAM is in DLL ON mode. 38. Assume no jitter on input clock signals to the DRAM 39. Value is only valid for RZQ/7 RONNOM = 34 ohms 40. 1tCK toggle mode with setting MR4:A11 to 0 41. 2tCK toggle mode with setting MR4:A11 to 1, which is valid for DDR4-2400/2666 speed grade. 42. 1tCK mode with setting MR4:A12 to 0 43. 2tCK mode with setting MR4:A12 to 1, which is valid for DDR4-2400/2666 speed grade. 44. The maximum read preamble is bounded by tLZ(DQS)min on the left side and tDQSCK(max) on the right side. Relationship". Boundary of DQS Low-Z occur one cycle earlier in 2tCK toggle mode which is illustrated. 45. DQ falling signal middle-point of transferring from High to Low to first rising edge of DQS diff-signal cross-point 46. last falling edge of DQS diff-signal cross-point to DQ rising signal middle-point of transferring from Low to High 47. VrefDQ value must be set to either its midpoint or Vcent_DQ(midpoint) in order to capture DQ0 or DQL0 low level for entering PDA mode. 48. The maximum read postamble is bound by tDQSCK(min) plus tQSH(min) on the left side and tHZ(DQS)max on the right side. 49. Reference level of DQ output signal is specified with a midpoint as a widest part of Output signal eye which should be approximately 0.7 * VDDQ as a center level of the static single-ended output peak-to-peak swing with a driver impedance of 34 ohms and an effective test load of 50 ohms to VTT = VDDQ. 50. For MR7 commands, the minimum delay to a subsequent non-MRS command is 5nCK. - 43 - Rev. 1.91 datasheet Registered DIMM DDR4 SDRAM 18. Physical Dimensions 18.1 1Gx8 based 1Gx72 Module (1 Rank) - M393A1K43BB0 Units : Millimeters Max 1.4 133.35 64.60 56.10 31.25 17.60 30.75 Max 1.4 3.35 1.4 0.10 126.65 4.30 3.85 0.10 C A E D B 1.50 0.05 Detail A 9.35 10.20 0.85 9.35 10.20 Detail C Detail B,E 2.1 2.6 0.25 2.6 2.1 B : 2.1 E : 2.6 0.6 0.03 Detail D 18.1.1 x72 DIMM, populated as one physical rank of x8 DDR4 SDRAMs D1 D8 D2 D3 D5 D6 D7 D4 D0 Address, Command and Control lines The used device is 1G x8 DDR4 SDRAM, Flip-Chip. DDR4 SDRAM Part NO : K4A8G085WB-BC** * NOTE : Tolerances on all dimensions 0.15 unless otherwise specified. - 43 - Rev. 1.91 datasheet Registered DIMM DDR4 SDRAM 18.2 1Gx8 based 1Gx72 Module (1 Rank) - M393A1K43BB1 Units : Millimeters Max 1.4 133.35 64.60 56.10 31.25 17.60 30.75 Max 1.4 3.35 1.4 0.10 126.65 4.30 3.85 0.10 C A E D B 1.50 0.05 Detail A 9.35 10.20 0.85 9.35 10.20 Detail C Detail B,E 2.1 2.6 0.25 2.6 2.1 B : 2.1 E : 2.6 0.6 0.03 Detail D 18.2.1 x72 DIMM, populated as one physical rank of x8 DDR4 SDRAMs D1 D3 D7 D6 D5 D4 D8 D2 Address, Command and Control lines The used device is 1G x8 DDR4 SDRAM, Flip-Chip. DDR4 SDRAM Part NO : K4A8G085WB-BC** * NOTE : Tolerances on all dimensions 0.15 unless otherwise specified. - 44 - D0 Rev. 1.91 datasheet Registered DIMM DDR4 SDRAM 18.3 2Gx4 based 2Gx72 Module (1 Rank) - M393A2K40BB0/M393A2K40BB1/M393A2K40BB2 Units : Millimeters Max 1.4 133.35 64.60 56.10 31.25 17.60 30.75 Max 1.4 1.4 0.10 3.35 126.65 4.30 C A E D B 3.85 0.10 1.50 0.05 Detail A 9.35 10.20 0.85 Detail B,E 2.1 2.6 2.1 0.25 2.6 B : 2.1 E : 2.6 0.6 0.03 9.35 10.20 Detail C Detail D 18.3.1 2Gx72 DIMM, populated as one physical rank of x4 DDR4 SDRAMs D1 D2 D3 D4 D18 D17 D16 D15 D5 D10 D11 D12 D13 D14 D9 D8 D7 D6 Address, Command and Control lines The used device is 2G x4 DDR4 SDRAM, Flip-Chip. DDR4 SDRAM Part NO : K4A8G045WB-BC** * NOTE : Tolerances on all dimensions 0.15 unless otherwise specified. - 45 - Rev. 1.91 datasheet Registered DIMM DDR4 SDRAM 18.4 2Gx4 based 4Gx72 Module (2 Ranks) - M393A4K40BB0 Units : Millimeters Max 1.4 133.35 64.60 56.10 31.25 17.60 30.75 Max 1.4 3.35 1.4 0.10 126.65 4.30 C A E B D 3.85 0.10 1.50 0.05 Detail A 9.35 10.20 0.85 Detail B,E 2.1 2.6 2.1 0.25 2.6 B : 2.1 E : 2.6 0.6 0.03 9.35 10.20 Detail C Detail D 18.4.1 4Gx72 DIMM, populated as two physical ranks of x4 DDR4 SDRAMs D1 D2 D3 D4 D5 D21 D22 D23 D24 D6 D7 D8 D9 D10 D25 D26 D27 D28 D32 D31 D30 D29 D15 D14 D13 D12 D11 D36 D35 D34 D33 D20 D19 D18 D17 D16 Address, Command and Control lines The used device is 2G x4 DDR4 SDRAM, Flip-Chip. DDR4 SDRAM Part NO : K4A8G045WB-BC** * NOTE : Tolerances on all dimensions 0.15 unless otherwise specified. - 46 - Rev. 1.91 datasheet Registered DIMM DDR4 SDRAM 18.5 2Gx4 based 4Gx72 Module (2 Ranks) - M393A4K40BB1 Units : Millimeters Max 1.4 133.35 64.60 56.10 31.25 17.60 30.75 Max 1.4 3.35 1.4 0.10 126.65 4.30 C A E B D 3.85 0.10 1.50 0.05 Detail A 9.35 10.20 0.85 Detail B,E 2.1 2.6 2.1 0.25 2.6 B : 2.1 E : 2.6 0.6 0.03 9.35 10.20 Detail C Detail D 18.5.1 4Gx72 DIMM, populated as two physical ranks of x4 DDR4 SDRAMs D1 D2 D3 D4 D5 D21 D22 D23 D24 D6 D7 D8 D9 D10 D25 D26 D27 D28 D32 D31 D30 D29 D15 D14 D13 D12 D11 D36 D35 D34 D33 D20 D19 D18 D17 D16 Address, Command and Control lines The used device is 2G x4 DDR4 SDRAM, Flip-Chip. DDR4 SDRAM Part NO : K4A8G045WB-BC** * NOTE : Tolerances on all dimensions 0.15 unless otherwise specified. - 47 - Rev. 1.91 datasheet Registered DIMM DDR4 SDRAM 18.6 2Gx4 based 4Gx72 Module (2 Ranks) - M393A4K40BB2 Units : Millimeters Max 1.4 133.35 64.60 56.10 31.25 17.60 30.75 Max 1.4 3.35 1.4 0.10 126.65 4.30 C A E B D 3.85 0.10 1.50 0.05 Detail A 9.35 10.20 0.85 Detail B,E 2.1 2.6 2.1 0.25 2.6 B : 2.1 E : 2.6 0.6 0.03 9.35 10.20 Detail D Detail C 18.6.1 4Gx72 DIMM, populated as two physical ranks of x4 DDR4 SDRAMs D1 D6 D32 D36 D2 D7 D31 D35 D3 D4 D8 D5 D9 D21 D22 D10 D25 D30 D29 D34 D15 D33 D20 D19 D26 D14 D13 D18 D23 D27 D12 D17 Address, Command and Control lines The used device is 2G x4 DDR4 SDRAM, Flip-Chip. DDR4 SDRAM Part NO : K4A8G045WB-BC** * NOTE : Tolerances on all dimensions 0.15 unless otherwise specified. - 48 - D24 D28 D11 D16